Verilog VCD Logger

This component implements a 1-bit digital data logger that creates a log file in the Verilog Value Change Dump (VCD) format. This file can be viewed by an external application such as GTKWave. Using an external waveform viewer may be more convenient than VMLAB's scope window when dealing with a very large amount of trace data.

Downloads

  • vcdlog-1.0.zip - Provides the logging component that writes to a VCD file.
  • vcdlog-1.0-src.zip - Contains the source code to the above vcdlog component.
  • vcdlog-1.0-test.zip - Contains an example VMLAB project using the vcdlog component. Also includes the "vcdlog.vcd" file produced by a sample run.

Usage

; To use this component, use the following component definition:
;
; X<Name> _vcdlog <Data>
;
; The component always writes to a file named "vcdlog.vcd", and if multiple
; component instances are used in the same project file, then the logged data
; from each instance is interleaved within the file. The instance <Name> is
; used as the variable name in the VCD file. <Data> is the single input
; bit being logged. The VCD file always uses a 1ns timescale, which will
; be adequate for all clock speeds under 1Ghz. The maximum number of vcdlog
; instances allowed per project is 94 (due to the single character ASCII
; identifiers used in a VCD file).

Example

Xcount0 _vcdlog pd0
Xcount1 _vcdlog pd1
Xcount2 _vcdlog pd2
Xcount3 _vcdlog pd3

Screenshot

The following screenshot shows GTKWave viewing the "vcdlog.vcd" file contained in "vcdtest.zip". Note that GTKWave allows individual signals to be combined into a bit vector, which is useful when analyzing parallel data buses and ports: