Digital Signal Delay

This component is a single bit digital buffer with user configurable propagation delays. When the input signal changes state, it must remain at the new logic level for the duration of the delay. If the input is changing faster than the delay, then these changes are ignored and do not affect the output. In this regard, the delay component also acts like a digital low-pass filter.



; To use this component, use the following component definition:
; X _delay(<RiseDelay> <FallDelay>) <DIN> <DOUT>
; The <RiseDelay> and <FallDelay> arguments specify two different delays for
; respectively propagating rising and falling edges of the input signal from
; the <DIN> pin to the <DOUT> pin. The <RiseDelay> is the minimum length of
; time that a logic 1 must be applied for on the input pin before showing up on
; the output. <FallDelay> serves the same purpose but for a logic 0 on input.
; The two delays need not be the same, and either or both can be zero. With a
; zero delay, the input signal will propagate on the next instruction cycle of
; the MCU (i.e. the minimum time resolution of the simulator). Note that for an
; UNKNOWN 'X' logic level on <DIN>, the propagation delay is always zero.


X _delay(4u 0u) DATAIN DATAOUT


The screenshot below shows the scope window that is produced by the example project in "". This project contains five delay component instances using a combination of different rising and falling delays. Note that VMLAB simulates a power on delay which results in a long "gap" in the simulated time step at the very beginning; depending on the rise or fall delay, this causes some components to produce an initial 'X' output while others produce the initial '1' that was already present on the DIN pin at time zero: