The Geometry of Synthesis is a new approach to higher-level synthesis of VLSI designs ("hardware") from behavioural descriptions written in a conventional ("software") programming language, called Verity. The main difference between GoS/Verity and other HLS tools is full support for functions in the programming language. This allows us to support things like:
We will soon advertise two postdoctoral research positions on a new EPSRC project titled "A higher-order approach to co-design", part of the "Working Together Across ICT" theme. It aims to develop semantic and type-theoretical models of high-level languages (functional, imperative, concurrent) in order to produce better compilation methods for heterogeneous architectures (CPU and FPGA).
The project has two tracks. One is focussed on theoretical aspects such as types for resource management and semantic models, particularly game semantics, and will be mainly carried out in Birmingham. The other is focussed on heterogeneous design, optimisation and applications, and will be mainly carried out at Imperial. The two sites will collaborate very closely and will jointly develop the 'Geometry of Synthesis' FPGA compiler.
The project is funded for 3 years, starting June 2013 and one post-doc will be employed at each site. The positions will be for an initial period of 18 months with the possibility of extension.
Candidates will need expertise in theory of programming languages (types and semantics) or reconfigurable computing (FPGA design and applications, EDA). We are particularly interested in candidates who are excellent thinkers and willing to learn and apply cutting-edge theory in order to solve practical problems and develop tools. A practical knowledge of functional programming language is essential.
The theory group in Birmingham and the FPGA group at Imperial are world-leading so we seek applicants with an excellent track record of research.
The salary in Birmingham will be in the range of £27,854-£36,298 and at Imperial in the range of £30,680-£39,130 per annum. The official adverts will follow soon but anyone interested is welcome to contact the co-investigators:
Dan R. Ghica, Birmingham
George Constantinides, Imperial
Also see EPSRC project summary at
The output of GoS is generic VHDL which can be (in principle) used in any conventional synthesis or simulation design flow. However, we test and run our code using Altera tool chains and FPGAs.