The Geometry of Synthesis is a new approach to higher-level synthesis of VLSI designs ("hardware") from behavioural descriptions written in a conventional ("software") programming language, called Verity. The main difference between GoS/Verity and other HLS tools is full support for functions in the programming language. This allows us to support things like:
- higher order functions (map, fold)
- a functional style of programming
- pre-compiled libraries
- foreign-function interfaces
- run-time services
- interfacing with legacy IP cores
The output of GoS is generic VHDL which can be (in principle) used in any conventional synthesis or simulation design flow. However, we test and run our code using Altera tool chains and FPGAs.