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Sudharsan Seshadri
  • Email: reachsudhar at gmail dot com or suseshad at ucsd dot edu
  • Phone: 412-418-6451

I am a Masters in Computer Engineering in Department of Electrical and Computer Engineering 
at University of California, San Diego.

I am currently pursuing my research work in Non-Volatile Storage Systems Laboratory (NVSL) under the guidance of 
To know more about the project done in my lab follow this link.

Areas of InterestsSoC Design, Non-Volatile Storage Systems, Computer Architecture


  • Masters of Science (M.S) in Computer Engineering from University of CaliforniaSan Diego [UCSD] (www.ece.ucsd.edu), Year: 2011 - 2013
  • Courses
    • CSE 240A Graduate Computer Architecture
    • ECE 260A VLSI Design
    • ECE 260B VLSI Intergrated Circuits 
    • CSE 237A Introduction to Embedded Systems
    • ECE 260C VLSI Advanced Topics
    • CSE 120   Principles of Computer Operating Systems
  • Bachelor of Engineering (B.E)Electronics and Communication Engineering (ECE) from Madras Institute of Technology, Anna University. http://www.mitindia.edu
    • CGPA   : 8.9/10.
    • Relevant Courses Taken : 
      • Intro to Computer Architecture, 
      • Principles of VLSI Design, 
      • Cryptography and Network Security, 
      • Digital Image Processing, 
      • Speech Processing Techniques

Work Experience

  • Worked as an ASIC Product Design Engineer-Intermediate in PMC-Sierra India Private Ltd from July 2007 - July 2011.
  • Teaching Assistant in UCSD Fall 2011 - Course CSE 140 - Digital Design
  • Graduate Research Assistant UCSD Spring 2011 - under Prof Steven Swanson

Publications : 

  1.  A 1 GHz Pipelined Low Power Floating Point Arithmetic Unit with Modified Scheduling for High Speed Applications published in International Conference on Signal Processing, Communication and Networking 2007 1-4244-0997-7, by K.M.Mukund, Sudharsan Seshadri, Janarthanan Devarajulu and M. Kannan, IEEE - ICSCN 2007, MIT Campus, Anna University, Chennai, India, Feb. 22-24, 2007, pp.377-381. [IEEE Link] [PDF]

Other Projects at MIT

  1. FPGA Implementation of Transmitter and Receiver blocks for the Store and Forward Link of ANUSAT Satellite (under Dr. Mala John, May –July 2006)
  2.  Analysis of JPEG 2000 Image Compression Standard Encoder and Decoder performance in MATLAB. (under Dr. Mala John, Dec 2006 – Mar 2007).

Projects at PMC-Sierra

  1. Bandwidth Estimation on a ONFi NAND Flash Interface to choose NAND Flash Controller IP Configuration.
  2. Product Validation of an ASIC in PMC-Sierra Canada Design Center.
  3. Project Lead for a 1Million Gate Block in an SoC - Design, Synthesis, Timing Analysis.


  • Cooking, Listening to Indian Classical Music