Publications

Theses

Milad Mohammadi. Thesis: Energy-Efficient Coarse-Grain Out-of-Order Execution, Concurrent VLSI Architectures Group, Stanford University, August 2015. [pdf]

Technical Reports

Yatish Turakhia, Subhasis Das, Tor Aamodt, William J. Dally. HoLiSwap: Reducing Wire Energy in L1 Caches. Technical Report 136, Concurrent VLSI Architectures Group, Stanford University, June 2015. [pdf]

Song Han, Jeff Pool, John Tran, and William J. Dally. Learning both Weights and Connections for Efficient Neural Networks . Concurrent VLSI Architectures Group, Stanford University, January 2015. [pdf]

Subhasis Das, Tor M. Aamodt, and William J. Dally. Reuse Distance Based Probabilistic Cache Replacement. Technical Report 134, Concurrent VLSI Architectures Group, Stanford University, June 2014. [pdf]

Milad Mohammadi, Song Han, Tor M. Aamodt, and William J. Dally. On-Demand Branch Prediction. Technical Report 133, Concurrent VLSI Architectures Group, Stanford University, September 2013. [pdf]

Subhasis Das and William J. Dally. Static Cache Way Allocation and Prediction. Technical Report 132, Concurrent VLSI Architectures Group, Stanford University, August 2012. [pdf]

R. Curtis Harting, Vishal Parikh, and William J. Dally. Energy and Performance Benefits of Active Messages. Technical Report 131, Concurrent VLSI Architectures Group, Stanford University, February 2012. [pdf]

Vishal Parikh, R. Curtis Harting, and William J. Dally. Configurable Memory Hierarchies for Energy

Efficiency in a Many Core Processor. Technical Report 130, Concurrent VLSI Architectures Group, Stanford University, February 2012. [pdf]

Posters

R. Curtis Harting, Vishal Parikh, William J. Dally.  The Utility of Fast Active Messages on Many-Core Chips.  Presented at Hot Chips 23, August 2011.  [pdf]
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