Downloadable  RESUME.pdf

SRIRAM MURALI                                                                Availability: December 2007

[Masters of Applied Science                                                                                            Research Assistant

Grad Student                                                                                                               CICSR 188                Dept of Electrical and Computer Engineering India                                                               



To pursue interdisciplinary research in the field of High Performance Computer Architecture and its Software Engineering requirements, the application to Grand Challenge Problems such as Protein Folding, Brain Modeling.


Sep 2008 - Aug 2010


 University of British Columbia Vancouver, Canada

(M.A.Sc.), Electrical and Computer Engineering 

 Velammal Engg. College, Anna University, Bachelor of Engineering (B.E.) in Electronics  and Communication



81.32% till 6th Semester


DAV Matric HSS Gopalapuram , Chennai, India. Higher Secondary Education



PS Senior Secondary School Mylapore, Chennai, India. Senior Secondary Education



Sep 2008 - Present           Research Assistant, Computer Systems Group.

                       My current area of research is on Virtualization of Multicore architecture and storage devices.

May 2006 - Sep 2008           Research Trainee working with Prof N Venkateswaran, Director,

Waran Research Foundation (WARFT), Chennai, India.


Worked on Memory In Processor (MIP) Node Architecture", VLSI design of higher-level functional units and a benchmark
simulator for high performance computers.




·       High Performance Interconnection Networks

·       Design of Special Purpose Supercomputing Architectures

·       Optimization and Performance Evaluation

·       Reliable and Low Power Architectures

·       Message Passing Interface

·       Wireless Networks



[1] Venkateswaran Nagarajan, Sriram Murali et al "Towards Node Architecture Designs for Realizing High Productivity Supercomputers" presented at the 23rd International Supercomputing Conference (ISC) '08, held at Dresden, Germany in Jun '08.

[2] Venkateswaran Nagarajan, Sriram Murali et al "On the Concepts of Simultaneous Execution of Multiple Applications on the Hierarchically based Cluster and the Silicon Operating System" presented at the Large-Scale Parallel Processing workshop held at the 22nd IEEE IPDPS '08, Miami, USA in Apr '08.

[3] Sriram Murali, Ramachandran Shankar, “Performance Evaluation of a vehicle Crash Control System using Image Processing”, International Symposium on Electronic Design Test and Applications
(pdf) (copyright)

[4] Sriram Murali, Arun Raman, “Missile Command – A Real time Missile Guidance Control”, International Conference on Intelligent and Advanced Systems (ICIAS 2007).
(pdf) (copyright)

Journal Publications:

[1] V. Nagarajan, Sriram Murali, et al "Towards Node Architecture Designs for Realizing High Productivity Supercomputers", ISC Wiley Interscience, Concurrency Computat.: Pract. Exper. 2008
[2]  Sriram Murali, Arun Raman, “Temperature Control of Dry Type Transformer using Fuzzy Logic”, LINK July 2007 Edition, IEEE Newsletter.

 Co-Authored WhitePapers :

N.Venkateswaran, Sriram Murali, Shrikanth Ganapathy, Murali Thiayagarajan “Analysis and Design Space Optimization of a High Performance High-Performance, Power-Aware Network based Node Architecture”, WARFT White-paper 2007.

N.Venkateswaran, Sriram Murali, Shrikanth Ganapathy, Murali Thiayagarajan “Performance Evaluation of a Large-Scale High level Parallel Processing Node Architecture for MIP SCOC”, WARFT White-paper 2007.

N.Venkateswaran, Sriram Murali, Shrikanth Ganapathy, Murali Thiayagarajan “Design of a scalable On-Node Communication Architecture for a High Performance Node Architecture”, WARFT White-paper 2007.



As a part of the requirements for the research program at WARFT we are required to submit a thesis encompassing all the research work done at the foundation.

Tentative Title:  Design Optimization of a Low Power, Reliable and Self Configuring On-Node Network for High Performance Node Architecture (Thesis )

          Ever increasing demand for high performance in Supercomputers posed by grand challenge applications Computational Fluid Dynamics, Protein Folding and Brain Modeling has a direct impact on the bandwidth support of the underlying architecture. The Memory In Processor paradigm provides this capability to handle higher mapping complexities to engender node architectures capable of achieving sub-petaops of computing power (at node level) with the design scheme called Heterogeneous Multi-Core Node (HMCN). However the overall performance depends on the communication capability within and across the cores. This work which develops a robust on chip interconnection model to address the requirements is divided into three phases as Design, Analysis and Optimization of the Node and Network architectures. A profound exploration of the interdependent design parameters of routing, switching, grouping strategy and quality of service leads to the evolution of the communication model termed as On Node Network (ONNET). Power awareness will be of great import due to reasons such as packing compactness and increased spiking of switches. Memory management must also be addressed by this model since it involves the logical integration of memory and processing capabilities of the node. Synthetic traffic is used for execution on the node (architectural simulator) to check the efficiency of the communication network generated. In sum, the proposed work will aid in developing an efficient, self managing and reliable communication model design to support the increased bandwidth requirement for high performance Memory In Processor (MIP) architecture and to optimize it taking the power and performance of operation into account.

   Expected to be completed by 05/ 2008

   Full papers, thesis, projects & other research works are available at the personal and group website


·       Virtualization of Cache Architecture: (Sep 08 – Present) Analyzing impact of multi-threaded application access on shared cache architecture using Virtual Machine Monitor.

 ·       MPI Library for Agitated Particle Motion Simulation – APMS: (Sep 08 – Dec 08) Wrapper for MPI based Particle motion analysis under external disturbance.

 ·       Wait-free Synchronization of Fault tolerant Data Structures: (Sep 08 – Dec 08) Implementation of non-blocking synchronization on fusible data structures for web servers and lock servers.

 ·        On-Node Network Architecture Simulator - ONNET SIMULATOR*: (Oct 07 - July 08) Simulator for analyzing on-chip interconnection network performance for MIP Node.

 ·       Design and Synthesis of Higher Level Functional units - ALFU DESIGN: (Feb 07 - Oct 07) Design of algorithm level functional units (ALFU) for MIP SCOC Node in Verilog and SystemC.

 ·        The Memory in Processor Simulator – MIPSIM*: (Mar 07 - Aug 08) Functional level simulation of MIP SCOC node, namely functional units and MIP instruction set using C and MPI.

 ·       Synthetic Benchmark for High Performance Clusters – BENSIM*: (Oct 06 - Aug 08) Tool for measuring supercomputing clusters performance using user-specified parameters generated by interdependent algorithms, and analyzing with profiling tools.



·      Operating System: Windows, LINUX, UNIX, Mac OS-X
Programming Languages: C, C++, Python, Verilog, VHDL, Visual Basic, MPI and basic Java
Scripting Languages : HTML, JavaScript, Perl
Mathematical modelling and CAD tools: MatLab and NetSim, Spice and Xilinx
Text and Graphics tools: LATEX, Open Office, MS Word, Smart Draw, Sigma Plot, Photoshop


·        Awarded Merit Certificate in Grade 12 for scoring 100% in Mathematics in the State Level Examinations.

·        Won first prize for paper presentation at various National Level Technical Symposiums        TELETEC ’07, Thiagarajar College of Engineering, Madurai; PHREAK ’06, Vellore Institute of Technology; PULSE ’06, Sri Venkateswara College of Engineering, Chennai.

·        Won first prize for Circuit Debugging at PULSE ’06, Sri Venkateswara College of Engineering, Chennai.

·        Won first prize for Technical Quiz at TELETEC ’07, Thiagarajar College of Engineering, Madurai.

·        Paper presentation, Student Chair, INNOWIZ ’06, a national level technical symposium at Velammal Engineering College, Chennai.

·        Network Gaming Coordinator, INNOWIZ ’06, a national level technical symposium at Velammal Engineering College, Chennai.

·        Jointly organized Dhi Yantra ’07, a Workshop on Brain Modeling and Supercomputing conducted by WARFT. The conference was attended by Dr. Kastoorirangan (Director of the National Institute of Advanced Studies, IISc, Banglore & Chairman(1994-2003) ISRO Space Commission/Secretary, Department of Space, Government of India), Dr. Henry Markram (Director of the Centre for Neuroscience & Technology and co-director of EPFL’s Brain Mind Institute), Prof N .Ranganathan, Editor in Chief, IEEE Transactions on VLSI(2003-04) and (2005-06), Dr. Vinoo Srinivasan(Intel Corporation, India) among others.


·        Cisco Certified Network Associate (CCNA) by Cisco Systems, Inc.

CISCO ID: CSCO11212630

·        Grade 3 Electronic Keyboard with Merit by Trinity College, London.


·         Student member, Institute of Electrical and Electronics Engineers (IEEE)  ID: 80535992


·        Telecommunication, Switching and Mobile Technology , Bharath Sanchar Nigam Ltd., Regional Telecom Training Centre, MM Nagar 20th to 24th June 2006



·        Attended an In Plant training on Webpage Designing and Internet Security , Pvt. Ltd., Training Centre, Mogappair East where I worked with Javascript and HTML

·        Performed Stage Shows at Crescent Engineering College in July 2005. (Orchestra – Keyboard)

·        Performed Stage Shows at Velammal Engineering College in Feb 2007. (Orchestra – Keyboard)

·        Performed On-air shows at reputed television channel and qualified till Semi finals.

·        Took Part and won prizes at various intercollegiate events such as Debates, Discussions and Network Gaming.

·        Participated at Inter-School light music programs and won first prize (Electronic Keyboard)



·        Completed Course in Networking(with CISCO Routers) in Sans Bound Solutions, India, Pvt. Ltd when I learned to configure CISCO Routers and Switches for several protocols such as RIP, OSPF and applications such as configuring Access Control Lists and Firewall

·        Secured Award for “Hundred Percent Attendance” in 1st year (2004-05) at Velammal Engineering College.

·        Sports coordinator of ECE Department for the year 2005-06

·        Jointly designed the website for the symposium INNOWIZ ’06, Department of Electronics and Communication Engineering, Velammal Engineering College.