News

Internship in University of Texas at Austin

posted Sep 14, 2016, 4:18 PM by João Bispo

Luís Reis spent 1 month in Austin, Texas in the UTA Portugal Colab 2016 Summer Internship.

Paper in CPC'16

posted Sep 14, 2016, 4:16 PM by João Bispo

Ricardo Nobre presented a paper in Compilers for Parallel Computing 20161.



1Nobre, R., Reis, L., & Cardoso, J. M. Compiler Phase Ordering as an Orthogonal Approach for Reducing Energy Consumption. Compilers for Parallel Computing (CPC'16). Valladolid, Spain

Participation in ACACES'16

posted Sep 14, 2016, 4:13 PM by João Bispo   [ updated Sep 16, 2016, 7:08 AM ]

Luís Reis participated in ACACES 2016, where he presented the poster Compiling MATLAB to OpenCL: Motivation, Approaches and Open Issues.

2016-acaces-luis
Luís can be (barely) found around the center, slightly to the right.

Paper in ARRAY'16

posted Sep 14, 2016, 4:12 PM by João Bispo

Luís Reis presented a paper in the ARRAY 2016 Workshop1.


1Reis, L., Bispo, J., & Cardoso, J. M. (2016, June). SSA-based MATLAB-to-C compilation and optimization. In Proceedings of the 3rd ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming (pp. 55-62). ACM.

Congratulations to Ali Azarian for his PhD degree!

posted Sep 14, 2016, 4:11 PM by João Bispo   [ updated Sep 15, 2016, 6:33 AM ]

On the 3rd of May 2016, Ali Azarian has defended his thesis "Task-Level Pipelining in Configurable Multicore Architectures" and is now a PhD.

The lab congratulates Ali for his hard work!

Ali Azarian, the defendent
Ali Azarian, the PhD candidate

The juri
The juri

Ali presenting his PhD work
Ali presenting his PhD work

LARA Tutorial at CSW'16

posted Sep 14, 2016, 4:09 PM by João Bispo

João MP Cardoso, Pedro Pinto, Ricardo Nobre, Tiago Carvalho, and João Bispo, presenting at CSW’2016, Porto, during the LARA Tutorial.

João Cardoso

Pedro Pinto

Ricardo Nobre

João Bispo

Tiago Carvalho

Micron PC with HMC

posted Sep 14, 2016, 4:06 PM by João Bispo

Arrived a PC, provided by Micron Technology, which contains a Kintex FPGA fitted with Hybrid Memory Cube (HMC) RAM.

Kintex FPGA

posted Sep 14, 2016, 4:04 PM by João Bispo

New addition to the lab, it has arrived a Kintex Ultrascale FPGA, from Alpha Data.

LARA Editor/IDE

posted Sep 14, 2016, 4:03 PM by João Bispo

We are developing an integrated development environment that can be used with LARA weavers. Stay tuned!


Pedro Pinto's PhD Admission Presentation

posted Sep 14, 2016, 4:02 PM by João Bispo

In the 2nd of February 2016, Pedro Pinto was officially admited as a PRODEI PhD student.

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