I am a Principal Engineer and Product Architect working on High Level Synthesis at Xilinx.
Previously, I worked in the Xilinx Research Labs investigating various aspects of system design for FPGAs.
You can reach me at firstname.lastname@example.org
University of Maryland, College Park
- High-level Synthesis for FPGAs
- FPGA platforms and system infrastructure
- Component-based modeling and design of embedded systems
- Design tools enabling refinement from models to implementation
- Formal system description (semantics, type theory, static analysis)
- The distribution of publication-quality research software
- Vivado HLS
Vivado HLS synthesizes C/C++ and SystemC into efficient pipelined FPGA implementations across a wide variety of applications, including video processing, wireless, control systems, medical imaging, and the data center.
- Ptolemy II
Ptolemy II is an component-based system modeling tool based on multiple models of computation in system design.
Vergil is a block-diagram user interface for Ptolemy II.
Copernicus generates code from Ptolemy II models using component specialization.
Diva is a Java-based infrastructure for system visualization and as basis
for graphical user interfaces.
Redemption Machine Project
A student-designed and built pinball redemption machine.