Shalini Ghosh

News (before joining Amazon in October 2020)


Currently I'm a Principal Research Scientist in Amazon Science, working in the Alexa AGI team.

Till August 2020, I was a Principal Scientist (Director) and the Leader of the Machine Learning Research team at the Smart TV division of Visual Display Intelligence Lab in Samsung Research America. Before this, from May 2018 - July 2019,  I also served as the Director of AI Research in the Artificial Intelligence center in Samsung Research America in Mountain View, reporting to Dr. Larry Heck.

Before May 2018, I was a Principal Computer Scientist in the Computer Science Laboratory at SRI in Menlo Park, reporting to Dr. Patrick Lincoln

I completed my PhD in 2005 at the Computer Engineering Research Center in ECE at the University of Texas at Austin. I worked with Prof. Nur Touba in the Computer Aided Testing (CAT) Laboratory. Previously, I did my MS from the Computer Engineering Department of University of California at Santa Cruz (UCSC). At UCSC, I worked with the Semiconductor Test Group. My MS Thesis advisor was Prof. F. Joel Ferguson.

In my undergraduate studies, I majored in Physics (Honors) from St. Xavier's College, University of Calcutta -- I minored in Mathematics and Chemistry.

I was invited to be a Visiting Scientist at Google Research in Mountain View, as part of the Google Visiting Faculty Program, for more than 1 year (July 2014 to August 2015). I worked on applying deep learning (Google Brain) models to problems in natural language understanding.

My contact email address is: "shalini DOT ghosh AT gmail DOT com"

Research Interests

I have worked on applying machine learning models to different domains. I am specifically interested in:

Selected Awards and Honors

Selected Talks and Interviews (recent)



PhD Thesis


Selected Patent Awards and Applications

Professional Services / Recognition/ Affiliations

 Projects at SRI

PhD Research (Computer Aided Testing Lab, University of Texas Austin, 2000 to 2005)

Studied the reduction of power consumption in concurrent error detection, for memory ECC checkers and low-power parity prediction circuits. Also studied how to reduce power in offline testing, for weighted pseudo-random BIST and scan testing.

MS Research (Semiconductor Test Group, UC Santa Cruz, 1998 to 2000)

Did MS thesis on fault modeling of interconnect opens using stuck-at tests, provided a statistical model for the conditions required for stuck-at tests to detect interconnect breaks in a circuit.

Internship Research during PhD

Official Mentoring/Hiring

Full-time employees:

Interns/International Fellows: