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Verilog

aptitude install iverilog gtkwave

module flip_flop(
D,
Q,
Q_not,
clk
);
input D;
input clk;

output Q;
output Q_not;

wire clk;
wire D;

reg Q, Q_not;


always @ (posedge clk)
begin : FLIP_FLOP
    if (D == 1'b1) begin
        Q <= 1'b0;
    end
    else if (D == 1'b0) begin
        Q <= 1'b1;
    end
    Q_not <= !Q;
end

endmodule

module flip_flop_tb;
reg clk,D;
wire Q, Q_not;

initial begin

    $dumpvars;

    $monitor ("Q=%b, Q_not=%b", Q, Q_not);
    clk = 0;
    #5 D = 1;
    #5 D = 0;
    #5 D = 1;
    #5 $finish;
end

always begin
    #1 clk = !clk;
end

flip_flop ff(
.D (D),
.Q (Q),
.Q_not (Q_not),
.clk (clk)
);

endmodule

iverilog -o flip_flop flip_flop.v
vvp flip_flop -vcd
gtkwave dump.vcd

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