HOSSAIN, Md. Sazzad

-keypoints

Analog Mixed-Signal, RF and mm-Wave Integrated Circuit Design;

Circuit Theory, Techniques and Optimization;

Schematic design, Electro-Magnetic simulation and Full custom Layout Design;

IC Design verification and Validation; Tapeout;

Chip Measurement and Testing

-design with semiconductor processes

ST Microelectronics: 28nm FDSOI CMOS, 0.13um SiGe BiCMOS;

TSMC: 40nm CMOS, 0.13um CMOS;

Fujitsu: 55nm CMOS;

AMS: 0.35um CMOS;

IHP Microelectronics: 0.25um SiGe BiCMOS (EPIC); 0.13um SiGe BiCMOS

-biography

I am working as an RFIC Designer (/Scientific Staff) at IHP Microelectronics (Frankfurt[O], Germany)-in the Millimeter-Wave and THz Sensors Circuit (MMTS) design unit, in-house SiGe-BiCMOS semiconductor design, fabrication facilities, measurement and testing. Previously, I was an IC Design Engineer at Sicoya GmbH (R&D Unit, Berlin, Germany) designing Ultra-high-speed electro-optic (Si-Photonics) TRX for the Server Interconnects. Sicoya is well well-known Photonic Integrated (ICs) products distributor to international tier 1 data centers, content, and services around the globe. And before then, I worked as an IC Design Engineer at CNRS-French National Centre for Scientific Research (UMR 7334-IM2NP Marseille) for an EU project on Fast-Simulation Mixed-Signal PLL design at 2.4GHz with system engineering support from German Colleagues at Fraunhofer ENAS. In addition, I worked at another unit of CNRS (UMR 5128-IMS Bordeaux) for the OCEAN 12 EU project, designing on Frequency Synthesizer 28nm CMOS FDSOI, especially designing Caliper PLL (dual loop instead of using power-consuming Fractional Dividers), analog LC-VCO, Ring Osc., and digital (Frequency Dividers, PFD, CP, LPF) for achieving low phase noise and jitter. The goal of this project is to design a PLL for GNSS connective Automotive vehicles at 1.1GHz to 1.5GHz and also applicable for four times its frequencies at 4.7 GHz, 5.2 GHz, and 6.3 GHz, and at the same time, it will work on WiFi at 5.16-5.76 GHz. During my master's studies, I have studied Millimeter-Wave Transformers for 60 and 79GHz CMOS Amplifier design.

I completed a Master’s (Engg.) at Hiroshima University, Japan, on Semiconductor Electronics and Integration Science, especially designing mm-wave analog CMOS ICs. My Bachelor's (Engg.) is from Rajshahi University of Engineering & Technology, Bangladesh, in Electrical & Electronic Engineering (EEE). During my undergrad thesis, I studied 4G LTE Advanced Full-duplex TRX modeling, Passive Optical Networks, and Fi-Wi networks.

-contacts

email: mshossain.dhaka.bd<a>gmail.com

-current work

IHP Microelectronics GmbH, Frankfurt Oder, Germany-

-Millimeter-Wave and THz Sensors Circuit (MMTS) Design Team

[0.13um SiGe BiCMOS (G2) IHP Process]

- Schematic and Layout Verifications, re-design (Top Level D-Band TRX ICs)

- Band-gap reference Circuits, LDOs, Power Detectors, and Front-end Automatic Gain Control (AGC) Circuit

- Ultra-High Speed 6G Wireless Communication

- D-band Antennas

- Ongoing....

Sicoya GmbH, Berlin, Germany-

-Electronic Integrated Circuit (EIC) Design Team

Electronic Circuit Design Team [0.25um SiGe BiCMOS IHP Process]

- Schematic and Layout Verifications (Top Level Electronic ICs, 100G TRX Project)

- Linear Driver (Variable Gain Amplifier), Inductive Peaking Analysis, BW Boosting, Problematic Nets Finding

- IDAC (Current Digital to Analog Converter), Mathematical Modeling

- DRC, LVS Check (Assura), Extraction (Quantus), Refined Extracted View Analysis

- Understanding the Electro-Optical Interconnects in 100Gb/s PAM4 TX for Server Interconnects

CNRS UMR 7334 (IM2NP-IO Labs), Marseille, France-

-Integrated Circuit and System (CCSI) Design Team

I. Tape-out @November 2022 [0.13um CMOS TSMC]

FastSim-EU Project: N-PLL design at 2.4GHz based on Fast Locking Event-Driven Model for IoT Applications

Project Description: https://anr.fr/Project-ANR-18-CE92-0047

+Fast Locking N-PLL design with Event-Driven Systematic Model.

+Event-Driven Systematic Simulator (EDAMS) executing [System-based support-Fraunhofer ENAS, Germany]

CNRS UMR 5218 (IMS Bordeaux Labs), Bordeaux, France-

Circuit and System (CAS) Design Team

II. Tape-out @June 2021 and Measured [0.35um CMOS AMS]

ULTRA Project: High-Frequency Transformer and Solenoid Inductor Design

+Horizontally H field (of the substrate) Inductor and Transformer Design, Pattern Ground Shield

+Spiral Inductor (Triangular, Rectangular, Planer, DNA alike) designed to understand Inductance, SRF, and Quality Factor

III. Tape-out @March 2021 and Measured [28 FDSOI CMOS ST Microelectronics]

OCEAN12 EU Project: 6.3GHz Frequency Synthesizer Design for GNSS and WiFi Applications

Project Description: https://cordis.europa.eu/project/id/783127

Analog and Digital Blocks:

+Caliper PLL (dual loop)- 4.7GHz-6.3GHz GNSS (4 times Freq.) and 5.16GHz-5.72GHz WiFi

+VCO (INV Chain Ring, Differential RING, and Dual Cross-Coupled LC type)

+Charge Pump (Conventional+ Bootstrapped)

+Passive Filters (2nd and 4th Order LPF)

+Frequency Divider (TSPC Block, 4bit and 8bit DE-COUNTER)

+Phase Frequency Detector (Tristate-PFD)

+SPI, Digital Frequency MIXER, PAD-RINGs, PCB Design

--------------------------

- Systematic Architecture and Model for PLL: Analog and Digital Blocks (MATLAB, VerilogA) and EDAMS-Event Driven Analog Mixed-Signal Simulator

- Transistor Level Design, Optimization, Schematic-Spectre, and Post-Layout Simulation, Corners, PVT variation

- DC, AC, TRANS, SP, Noise Analysis (PSS, pnoise, hb, hbnoise), etc.

- DRC, LVS Check (Calibre, Assura), Extraction (PEX, Quantus, SPICE), Full Custom Layout Design, Top Level Simulation, Verifications, Phase Margin, Jitter and FOM

- Tape-outs, Measurements (a few) and PCB Schematic Design only

- 2.4GHz PLL prototype for IoT and Zigbee Application

- 6.3GHz Caliper (dual loop) PLL prototype for GNSS Connectivity Automotive Vehicle and WiFi Application (One Chip-Dual Operation)

Frontier Integrated System Laboratory-FIS, Hiroshima, Japan-

FIS Laboratory, Graduate School of Advanced Sciences of Matter

Supervision: Prof. Minoru Fujishima, Prof. Takeshi Yoshida, Prof. Kayoa Takano

M.Sc. Thesis (Device): “Design of CMOS On-Chip Transformers for Millimeter-Wave Amplifiers”. [Fujitsu 55nm CMOS]

- Analog Schematics and Layout Design-60GHz and 79 GHz Transformer Coupled Amplifier

- Millimeter-Wave Transformer Design (Stacked and Planner Type)

- L-C-L Coupled and Transformer Coupled Matching Network, LNA, PA (Basic Understanding)

- MATLAB Modeling, Simulation, and Optimization

- EM Simulation of Small Transformer at MOMENTUM and HFSS

- 3dB BW, High Gain Amplifier, Noise Analysis, Noise Figure, Output Power, PAE

Training/Short Coursework:

[1] (August 2017) at Research Institute for Nanodevice and BioSystems, Hiroshima, Japan

- Fabricated of a MOS Capacitor, Take a Measurement result of C-V Curve of MOS capacitor

[2] (May 2017) at Micron Memory Japan, Inc., Hiroshima, Japan

- DRAM Semiconductor Fabrication Company: LSI Process System has been overlooked, Memory

Process Engineering of SDRAM (DDR4 DDR3), Clean Room Exploration

-academic background

M.Sc.(Engg.)(2016 October. 01 - 2018. September. 20)

Hiroshima University, Higashi-Hiroshima, Japan.

Dept: Semiconductor Electronics & Integration Science

Faculty: Graduate School of Advanced Sciences of Matter

Major: mm-Wave CMOS Integrated Circuit Design (Devices)

Japanese Government Scholarship (MEXT/ Monobukagakusho), (2016-2018) for Master's Program.

B.Sc. (Engg.) (2010 March. 7 - 2015 March. 02)

Rajshahi University of Engineering & Technology,

Dept: Electrical & Electronic Engineering

Faculty: Electrical & Computer Engineering

Major: Optical-Wireless Communication (Systems)

Bangladesh Government Technical Scholarship, (2010-2014) for Bachelor's Program.

H.Sc. (2007 July. 22 - 2009 July. 25)

Notre Dame College, Dhaka

S.Sc. (2005 January. 01 - 2007 June. 12)

Rajuk Uttara Model School & College, Dhaka

Bangladesh Government Board Scholarship, (2007-2008) for Secondary School Certificate Exam.

-job experiences

[8] RFIC Designer (MMTS team-R&D Unit), IHP Microelectronics, Frankfurt[O], Germany. [Present]

[7] IC Design Engineer(ECD team- R&D Unit), Sicoya GmbH, Berlin, Germany.

[6] IC Design Engineer(CCSI team-R&D Unit), UMR 7334 IM2NP, French National Centre for Scientific Research, Marseille, France.

[5] IC Design Engineer (CAS team-R&D Unit), UMR 5218 IMS, French National Centre for Scientific Research, Bordeaux, France.

[4] Lecturer, Dept. of Electrical & Electronic Engineering-National Institute of Textile Engineering & Research, Dhaka, Bangladesh.

[3] Lecturer, Dept. of Electrical & Electronic Engineering- The International University of Scholars, Dhaka, Bangladesh.

[2] Lecturer, Dept. of Electrical & Electronic Engineering-Z. H. Sikder University of Science & Technology, Sharitpur, Bangladesh.

[1] Master's Research Student, Frontier Integrated System Laboratory, AdSM-Hiroshima University, Hiroshima, Japan.

-application materials/hard skills

Integrated Circuit Design Tools- CADENCE, ADS [Schematic Design (Spectre Virtuoso, LTSpice), Optimization (MATLAB, Golden Gate), Virtuoso Layout Editor, EM Model (2.5D, 3D)]; Parasitic Extraction (PEX, Quantus) DRC-Design Rule Check, LVS-Layout vs. Schematic(Assura, Calibre, PVS), Tape-out

Basic Circuit Simulation Tools- PSpice (Node Analytical); EasyEDA; KiCAD; KLayout; Proteus Circuit Simulator

Electromagnetic Environment Tools- MOMENTUM; HFSS; ADS (RF/uWave/FEM)

Systematic-Numerical Analysis Tools- MATLAB; VerilogA; EDAMS (PLL only)

Programming & Reporting Tools- C; Python; MS Office; Latex

-publications/projects

EU Project Works @IHP, Frankfurt[O]:

[7] Tape-Out at December 2023: 140GHz D-band AGC (Automatic Gain Control) for the 6G front-end TRX [IHP 130nm SiGe[G2] Bi-CMOS]. [Awaiting for Chip return]

[6] Tape-Out at December 2023: Band-gap Reference circuits and LDOs for the resilient biasing wrt. PVT [IHP 130nm SiGe[G2] Bi-CMOS]. [Awaiting for Chip return]

EU Project Works @IO Lab-IM2NP, Marseille:

[5] Tape-Out at November 2022:N-PLL design at 2.4GHz based on Fast Locking Event-Driven Model for IoT and Zigbee Applications [TSMC 130nm CMOS]. [Chip already returned and planning for on-wafer measurement]

(2) Mathieu Guerin, Fayrouz Haddad, Md Sazzad Hossain, Ivan Kaufmann, Christian Hedayat, Wenceslas Rahajandraibe, Remy Vauche, Ulrich Hilleringmann, “Efficient Co-Design Methodology combining Fast and Accurate System-level Simulations with Transistor-level Characterization”, 30th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Istanbul, Turkey 4-7 December 2023

Link: <https://ieeexplore.ieee.org/document/10382733>

EU Project Works @IMS Lab, Bordeaux:

[4] Tape-Out at March 2021: Frequency Synthesizer Design in 28nm CMOS FDSOI (ST Microelectronics); 4.7GHz-6.3 GHz Galileo (GNSS) and 5.16GHz- 5.72 GHz WiFi applications. [Chip already returned and measurement done]

[3] Tape-out at June 2021: Layout Design: Transformer and Solenoid Inductor design at 0.35um CMOS AMS Technology; Properties check on Micro-wave and Millimeter-wave range. [Chip already returned and measurement done]

(1) Md Sazzad Hossain, Mateus Bernardino Moreira, Francois Sandrez, Francois Rivet, Herve Lapuyade, Yann Deval, “Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology”, 13th IEEE Latin America Symposium on Circuits and Systems, Puerto Varas, Chile, March 1 – 4, 2022

Link: <https://ieeexplore.ieee.org/document/9789073>

Master’s Thesis@ FIS Lab, Hiroshima

Thesis Title: “Design of CMOS On-Chip Transformers for Millimeter-Wave Amplifiers”, August. 2018. Projected by MIE Fujitsu Semiconductor Inc.-MIFS. (LSI 55nm NMOS Process) & Frontier Integrated System Laboratory, Graduate School of Advanced Sciences of Matter-AdSM, Hiroshima University, Japan.

[CMOS: Complementary Metal Oxide Semiconductor FET]

Project Works @FIS Lab, Hiroshima:

[2] Schematic and Layout Design (Amplifier): 60GHz smaller dimensional wide band CMOS Amplifier design; 79GHz smaller dimensional wide band CMOS Amplifier design; 79 GHz mm-wave Capacitive Coupling Differential amplifier with L or Pi type Matching Network.

[1] Schematic and Layout Design (LNA): Three-stage single-ended Capacitive Coupling LNA design at low power consumption at 80GHz.

Bachelor’s Thesis@ EEE RUET, Bangladesh

Thesis Title: “Future Internet Technologies: Hybrid CO-OFDM-TWDM PON and WLAN System for FiWi Amelioration”, November 2014. Department of Electrical & Electronic Engineering, Rajshahi University of Engineering & Technology-RUET, Bangladesh.

[CO-OFDM: Coherent Optical-Orthogonal Frequency Division Multiplexing, TWDM: Time-Wavelength Division Multiplexing, PON: Passive Optical Network, WLAN: Wireless Local Area Network, Fi-Wi: Fiber-Wireless]

IEEE Student Member #ID 97529305

Google Sites

Report abuse