Chips with no salsa!





I am part of the Robust Low Power VLSI (RLPVLSI) group headed by Dr. Ben Calhoun. My research interests are in Robust SRAM design, particularly alternative bitcells, and SRAM design optimization for sub-45nm technologies.


1. J. Wang, S. Nalam, and B. H. Calhoun, "Analyzing Static and Dynamic Write Margin for Nanometer SRAMs", ISLPED, August 2008

2. S. Nalam and B. H. Calhoun, "Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T", CICC, September 2009

3. M. Bhargava, S. Nalam, B. H. Calhoun, K. Mai, "An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization", TECHCON, September 2009

4. S.Nalam, M. Bhargava, K. Ringgenberg, K. Mai, and B. H. Calhoun, "A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes", ICCD, October 2009

5. S.Nalam, V. Chandra, C. Pietrzyk, R. Aitken, and B. H. Calhoun, " Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation", ISQED, 2010

6. R. Mann, S. Nalam,  J. Wang, and B. H. Calhoun, " Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM", ISQED, 2010

7. S. Nalam, M. Bhargava, K. Mai, and B. H. Calhoun, “Virtual Prototyper (ViPro): An early design space exploration and optimization tool for SRAM designers”, DAC 2010

8. J.Wang, S. Nalam, Z. Qi, M. Stan, and B. H. Calhoun, "Improving SRAM Vmin and Yield by Using Variation-aware BTI Stress", CICC 2010

9. R. W. Mann, J. Wang, S.Nalam, S. Khanna, G. Braceras, H. Pilo, and B. H. Calhoun, "Impact of circuit assist methods on margin and performance in 6T SRAM", Journal of Solid State Electronics, 2010  . 

10. S. Nalam, V. Chandra, R. Aitken, and B.H. Calhoun, “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs”, DATE, 2011  

11. S. Nalam and B. H. Calhoun, “5T SRAM with Asymmetric Sizing for Improved Read Stability”, JSSC, 2011