Sarma Vrudhula at ASU‎ > ‎Teaching‎ > ‎

Digital VLSI Testing

Designing and manufacturing an integrated circuit, or a subsystem or an entire system is just the half of the endeavor. Determining whether or not it is behaving according to the specification or performing its intended function is the other half. This graduate level course aims to provide a comprehensive and detailed treatment of digital systems testing. It will first cover the practical aspects of how testing is carried out, assuming the stimuli are known. This will include full scan design and boundary scan, and Built-In Self Test. Then the course will also cover the what of testing: fault models and logic and fault simulation; combinational and sequential test pattern generation; memory testing; delay testing; and other Design for Testability (DFT)techniques. The course will cover both the practical aspects of testing as well the theoretical and algorithmic aspects of the testing techniques. 

Prerequisites:
  • A undergraduate course covering the essentials of logic design including Boolean algebra, SOP and POS forms, design of basic combinational and sequential logic components (e.g. flip-flops and latches and their characteristics), combinational function minimization, finite state machine design. 
  • Strong background in data structures and algorithms, good experience in programming in  C and/or C++ can be helpful. Programming exercises will be done in Python - a extremely easy to learn and powerful interpreted, object-oriented, high-level programming language. 
  • Elementary UG background in linear circuits and knowledge of basic electrical concepts.
  • This course also requires some mathematical maturity, especially in discrete mathematics. 
Syllabus:
  1. Motivation & Terminology: Types of failures, physical defects, taxonomy of fault models, fault activation and detection, fault simulation, test generation, cost of testing and not testing. Testing terminology. 
  2. Methods of Test Application: Full scan design, structure of scan FFs and Latches, organization of scan chains, test application via scan chains. Techniques to design scan chains to reduce test time and cost. Built-in SelfTest by on-chip pattern generators. LFSR theory and design. Custom pattern generators. Response compression and analysis. BIST methodologies.
  3. Logic and Fault Simulation (FS): Event driven logic simulation, description of faulty and fault free circuits, fault collapsing, basic procedures used for fault simulation, parallel, deductive, concurrent and critical path tracing methods.
  4. Test Generation (TG): Description of fault-free & faulty circuit; Composite value systems; fault activation & propagation; TG basics: implication analysis; complete TG algorithms: D-algorithm, PODEM/FAN; non-structural TG.  Challenges to Seq. ATPG. Fault simulation of sequential circuits; TG using linear iterative array model of sequential circuits. Experiments on sequential machines
  5. Delay Faults Test Generation: Taxonomy of delay faults; gate and path delay faults; robust and non-robust tests; combinational TG for PDFs; FS for delay faults; TG for delay faults in sequential circuits. 
  6. Memory: Design of a SRAM cell; Various types of memory faults; Classical tests: 0/1, checkerboard, GALPAT; March tests; 
  7. Boundary Scan: Boundary Scan architecture for testing board level interconnects. Boundary scan instruction set and test procedures. 
References (Partial List)
  • Testing of Digital Systems, Niraj Jha and Sandeep Gupta. Cambridge University Press 2003.
  • Essential s of Electronic Testing, Michael L. Bushnell, Vishwani D. Agrawal. Kluwer Academic Publishers 2000. 
  • VLSI Test Principles and Architectures, Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. Morgan Kaufmann Publishers. 
  • Digital Systems Testing and Testable Design, Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman. IEEE, 1994. 
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