Professional


 

I am a Doctoral student at the University of Texas. My advisor is Prof. Jacob Abraham. My focus of research is native-mode self test of processors (a.k.a. software-based self test).  

 When I say test, I mean manufacturing tests. These are tests that verify whether a fabricated chip (silicon hardware) is working according to expectations.  Generally, this is done using DFT (design for test) based methods. These methods include having scan flops in the design. Scan flops allow values to be directly loaded/read from/to the external environment.  However, I am more interested  in native-mode self tests (a.k.a software-based self tests). These kinds of tests use the intelligence of the device under test. For example, instructions can be loaded into the cache  to  test  a processor. A processor  can also test the peripherals  using  instructions. However, test generation for  native-mode testing is a hard problem. 

During my Master's at University of Colorado, I worked in the area of formal verification. To be more precise, I was interested in dealing with Buchi automata. These automata are primarily used in linear time logic (LTL)  based model checking. Prof. Fabio Somenzi guided me during this period. 

 If you are interested  in these topics you can read some of my  publications given here. Please read the disclaimer below before downloading any articles.

Publications 

Disclaimer

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted, copied or distributed without the explicit permission of the copyright holder.

Please note that the definitive versions of these papers are the published versions in the respective proceedings. The electronic versions are provided here as a courtesy, and, in some cases, there may be differences between the electronic copy provided here and the published version. We believe that all of the differences are either formatting differences or copy-editing changes. If you cite any of these papers, please cite the published version rather than providing a URL to this website.

  • S. Gurumurthy, R. Vemu, J. A. Abraham and D. G. Saab, ’Automatic generation of instructions to robustly test delay defects in processors’, European Test Conference (ETS ’07), pages 173 – 178, 2007 [pdf]
  • S. Gurumurthy, R. Vemu, J. A. Abraham and D.G.Saab, ‘Using static timing analysis and verification engines to generate native-mode tests for small delay defects’. Latin American Test Workshop, (LATW '07), 2007 [pdf]
  • S. Gurumurthy, S. Vasudevan and J. A. Abraham, ‘Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor’. International Test Conference (ITC '06), Paper 27.3, 2006 [pdf]
  • S. Gurumurthy, S. Vasudevan and J. A. Abraham, ‘Automated Mapping of Pre-Computed Module-Level Test Sequences to Processor Instructions’. International Test Conference (ITC '05), Paper 12.3, 2005 [pdf]
  • S. Gurumurthy, O. Kupferman, F. Somenzi and M. Y. Vardi. ‘On Complementing Buechi Automata’. Conference on Correct Hardware Design and Verification Methods (CHARME ‘03) [pdf]
  • S. Gurumurthy, R. Bloem, and F.Somenzi, ‘Fair Simulation Minimization’. Fourteenth Conference on Computer-Aided Verification (CAV ’02), pages 610-623, 2002 [pdf]