The subject of this section of my website is the development of accurate circuit simulation SPICE models for power MOSFET interelectrode capacitances and transient effects. Warning! It is quite long and wordy! These pages were started in April 2013 and were then under development but now is on "hold" due to my lack of available time. It includes some "intro" stuff on the subject that may be of interest. Update 2/2/2014: It turns out that I had developed a very basic concept about the equivalency of these NMOS gate capacitances to a parasitic PMOS device's capacitances in my previous position at Bell Labs (in about 1985 or so). Although I think my concepts there were entirely correct I didn't have the opportunity at that time to experimentally validate them in detail. As a reference for my subsequent (published) work, please see "An
Accurate Model For Power DMOSFET's Including Interelectrode
Capacitances," Scott, R. S.; Franz, G. A.; Johnson, J. L., IEEE
Transactions on Power Electronics, vol. 6, no. 2, April 1991.No longer completely "on hold" for the last few days. I've added a (19 year old) recently-touched-up, downloadable curve-fit model (but NOT a SPICE model!) for power MOSFET capacitances. Look near the bottom of my Curve Fit Power MOSFET Capacitance Model page for the downloadable Excel file. If you're reading this page you probably know a bit about power MOSFETs and their uses. If you don't have a clue about these devices you may find it a bit harder to follow. A Bit of History Back in about 1990 I had just begun working on device and switchmode converter circuit modeling at GE for a power conversion design group. At the time there were two important and urgent issues I wanted to address regarding existing SPICE models. The first (and, in many ways, simplest to address) was that "soft reverse recovery effects" for diffused junction diodes were not included in any SPICE models at that time. If you don't know what "soft recovery" is you may not need to worry about it - it isn't always essential in understanding some power MOSFET capacitance issues. At the time, the existing diffused junction diode models yielded grossly incorrect SPICE simulation results in many cases. Sometimes simulated voltage spikes during diode turn-off were up to thousands of volts, whereas the real circuits showed voltage spikes of only a few volts or less. I solved this problem by creating a much more realistic SPICE diode model (see Advanced Diode Recovery Model ). I also sometimes used this diode stored charge model for power MOSFETs (for the MOSFET parasitic "body diode" capacitance) as a part of my next big goal... My second, and bigger, challenge was that vertical power MOSFET SPICE models available then incorporated interelectrode capacitances that were often not even within an order of magnitude of being correct. While there were some concepts extant that could be reasonably useful for typical switching events (the brilliant "gate charge" idea), this typically produced only models where the small signal Cgd capacitance was a constant value - that is, it didn't vary tremendously with both Vds and Vgs voltages as I knew it actually did. So I wanted to improve this situation and create a more realistic SPICE capacitance model for these transistors. By the way, the "DC" models for power MOSFETs, back in 1990, were "pretty much OK". That is, the steady-state current vs. voltage (sometimes called IV) characteristics could be modeled in a reasonably realistic way using standard SPICE models having appropriate parameter values. For example, here's an old measured/modeled IV comparison I found in my files... Pretty reasonable agreement between the measured data and the model. But the available power MOSFET CAPACITANCE and body diode reverse recovery model deficiencies meant (to me, at least) that you couldn't really trust any SPICE circuit simulation that included a switched power MOSFET. If the SPICE models' interelectrode capacitances were far from correct then you couldn't reliably predict switching times or gate drive requirements. Power MOSFET Capacitance Models Circuit designers know that one of the most critical interelectrode capacitances is the Cgd (gate to drain) capacitance. This is because, in a typical switching circuit, this capacitance is connected between the high voltage drain output of the switch and its low voltage input control terminal, the gate. Because of the (typically) large voltage gain of a switchmode transistor, the effect of this Cgd "feedback" capacitance on the input gate terminal is greatly increased due to the so-called "Miller effect". I won't describe the Miller effect here... if you're not familiar with it you'll need to investigate this widely-described circuit concept elsewhere. Below I'm showing a typical plot of measured small signal interelectrode capacitances vs. Vgs and Vds for a very old IRF450R power MOSFET (measured in 1993!). You can see that these capacitances are very far from constant. Yet the best SPICE models available then usually assumed constant capacitances or were not based on actual device measurements (and had other big deficiencies). A constant model value for Cgd, for example, was typically derived from a so-called "gate charge" measurement (again, I won't describe this concept here, you'll need to look it up elsewhere). Nobody at the time (and for a couple of decades, other than me, I think), had even figured out how to measure these small signal power MOSFET interelectrode capacitances while varying both Vds and Vgs*. Amazingly, it isn't "rocket science" but it required a special bias circuit that was slightly challenging to design, make, and use properly. * Actually I've found maybe just a few papers before 2010 (three or less if I recall correctly) where the authors attempted to do such measurements, but even these were either extremely limited in bias values applied or had some other problems. Oddly enough there were many, many papers out there describing various, usually very simplistic, SPICE models for power MOS capacitances. But essentially none of them actually did the small signal MOS measurements needed to confirm their models. Instead, they tended to use the clever, but also limited, "gate charge" characterization method (pretty simple to set up but does not yield detailed information at arbitrary bias conditions or the inspiration for a more correct physically-based model). You can clearly see that the interelectrode capacitances for this IRF450R transistor are highly nonlinear in both Vgs and Vds. For realistic circuit simulation models, NONE of these capacitances should be approximated as constant! If you're in the power conversion business and your folks can't produce or understand, in detail, power MOSFET capacitance measurements like the one above (which I did over two decades ago!), you REALLY need to step back and ask what the hell is wrong with what you're doing! You may note that these measured values are mostly for negative values of Vgs (the transistor is OFF). Try not to worry excessively about that right now; there's very good reasons. They are 1) you can't practically measure the small signal on-state capacitances vs Vgs and Vds in such detail (although gate charge measurements are a very good large-signal start) and 2). The gate capacitances are primarily due to a parasitic PMOS device - measuring at negative gate voltages exhibits its properties much better. In addition to the depletion-region capacitance results shown above, it is also possible to improve the reverse recovery model for the MOSFET "body diode". Such reverse recovery only occurs if the body diode is forward biased at some point (drain negative with respect to source), then transitioned to its normal operating mode (drain positive to its source). 25 years or so ago I developed a "soft recovery" model for junction diodes (see above). The measurement and modeling techniques I developed then can also be used as a simple model improvement for soft reverse recovery effects in the body diode of power MOSFETs (see Advanced Diode Recovery Model ). Now I've set myself the goal of re-creating, and possibly even improving on, the power MOSFET capacitance models I developed 20 years or so ago. Why Measure MOS Capacitances at Mostly Negative Gate Voltages? While this choice may seem at first inadvisable, there are actually good reasons. Here they are: The first, and possibly most important reason, is that it is impractical to measure all power MOS capacitances while the gate is biased above threshold. Since the device is then turned ON and has a very low drain-to-source (Rds) resistance, you can't really measure small signal capacitances in the ON state. Very simply, any comprehensive capacitance measurements will be made impossible by this low-valued Rds resistance (I've actually seen exactly ONE paper where someone has tried this... a very brave engineer - yet not very successful). But there are OTHER reasons too. Another important reason is that (per my model described below, and described in "An Accurate Model For Power DMOSFET's Including Interelectrode Capacitances," Scott, R. S.; Franz, G. A.; Johnson, J. L., IEEE Transactions on Power Electronics, vol. 6, no. 2, April 1991) the very important n-channel power MOS small-signal gate capacitances are actually and largely due to a parasitic PMOS device consisting of the lightly doped drain, gate, and p-body. To make a long story shorter, would you characterize such a PMOS device using an applied positive gate voltage or with a negative gate voltage? Please read further to understand the argument before you decide my statement is idiotic! In fact, measuring power nMOS capacitances at negative Vgs tells us a LOT about the critical gate-to-lightly-doped drain characteristics (such as the important drain doping profile and how the gate capacitances vary with Vds and Vgs voltages). There IS a "sort-of" reasonable way to characterize (large signal, at least) nMOS gate capacitance in the ON state (positive Vgs). This is the wonderful "gate charge" test method. Brilliant! But it still misses a lot of the interesting device physics - although this can be improved by starting a gate charge measurement at a large negative voltage (see my old paper referenced above). Some important device insights can only be revealed by doing this. I realize this negative Vgs capacitance measurement method is very unintuitive. But please think it through and research my physics arguments. In addition, engineers usually believe that devices should be characterized under the same conditions they are used in with real power circuits (which are typically zero to above threshold gate biases for nMOS's). But this "obvious" device characterization concept is not always true! You can learn a lot more things about an nMOS power MOSFET capacitances by using negative gate bias that can't be revealed by measuring only during its usually-employed positive Vgs bias characteristics. Another similar and instructive example I've encountered - people have traditionally measured diode reverse recovery using a constant negative-going current slope because this is what the diode current looks like in a typical inductively-fed application. But the series inductance usually involved in such a test, by increasing test circuit ringing, can actually totally OBSCURE important soft recovery effects that can only be seen by using a more resistive test voltage source (with LOW inductance). In order to realistically characterize a diode you may NEED to use test circuits that are NOT AT ALL like the inductively-fed conditions seen in typical circuit applications. Unintuitive, but think about it! My "Lost" MOSFET Capacitance Models I have some difficulties, however, in achieving this goal. It turns out that, for a variety of reasons, I've lost almost all the work I did on MOSFET capacitance modeling way back in the early 1990s. Some of the reasons are: 1. When I left GE (where I did much of my MOS modeling work) I didn't intentionally take any of my MOSFET model files with me (although my boss said he didn't care... but I'm pretty careful about being ethical with intellectual property). 2. Still, I had just a few files unintentionally left on my PC or floppies from when I took them home to work on (such as the measured values for the IRF450R plot above). But all the model description files were either old, incomplete, corrupted, or I no longer had the software to use them. For example:
UPDATE 4/3/2013: I just completed an extensive search of my old files to see if there was still a Saber physics-based model file somewhere on my hard disk. I couldn't believe I didn't keep a copy of this model. But, unfortunately, I confirmed that I really didn't save this Saber model. However, I discovered that I DID save a couple of other types of files! These were files used in MathCad and in a curve-fitting program I used back then (my last update was from 1995) called "Scientist" from MicroMath (very high quality software). It appears that a few of the MathCad files are compatible with my "slightly more modern" version of that app (although they need Notepad++ corrections to make them readable, given some unix-to-windows file conversion mistakes). The "Scientist" curve-fit model formulas and parameters amongst these files just "might" allow me to create an updated curve-fit MOSFET capacitance model much more quickly than I thought (maybe just a few weeks... but I've got other business to take care of first in the near future)! Update 2/2/2014: I've added a (19 year old) curve-fit power MOSFET capacitance model. Look near the bottom of Curve Fit Power MOSFET Capacitance Model for a downloadable Excel model file. Power MOSFET Capacitance Modeling Methods and Tasks Below are some comments on what I think I need (or want) to do now to try to rebuild/improve my ancient power MOSFET capacitance models. Task #1: Create a Power MOSFET Capacitance Measurement Capability All of my early 1990's power MOSFET capacitance models, regardless of the genesis of the models' equations, were based on fitting the model parameters to actual MEASURED capacitances of real power MOSFET devices. But I no longer have the capacitance measurement setup I built 20+ years ago. And it requires some fairly costly test equipment and the building/design of an appropriate bias test box that uses very specialized capacitors, etc. None of these requirements are particularly easy or affordable for a guy who is doing this more-or-less as a hobby. Fortunately, I already have the most expensive piece of equipment needed: an appropriate LCR-type meter (see HP 4276A LCZ meter on my "boatanchor" pages). I also need a high voltage variable voltage source (for the drain bias) and a low voltage variable voltage source (for the gate bias). It would be nice to be able to control these using a program like Labview using USB or GPIB inputs, but it's not necessary if only a few transistors will be measured (it's very time and labor-intensive otherwise). I've got an ancient Labview license, a very old GPIB controller card for a PC, and "some" of my sources can use GPIB control. But, for now, computerized control is only a project to be considered in the future. Still, this measurement capability is ESSENTIAL for the creation of new individual component power MOSFET capacitance models. That is, it is an absolute prerequisite. To make a long story shorter, the transistor data sheets just don't have the detailed information needed to create a realistic capacitance model and you can't, in any practical way, figure out what the capacitances of a real device "should" be using only theory. There's just too many design unknowns and also two or three-dimensional effects. Practically, you REALLY need to create your models based on actual capacitance measurements of the devices being modeled! Tasks #2-#4 Create New/Updated Power MOSFET MOS/Junction Depletion Capacitance Modeling Techniques (Formulas)"Way back when (early 1990's)" I actually developed three different types of capacitance model formulations for power MOSFET circuit simulation. I will probably want to try all three methods again to see which one is the most useful in this new day and age. You can see example results from each of these old models on Slide #7 at My Background Visual Presentation. Following is a short description of these three methods. Task #2: Use a Standard SPICE Parasitic PMOS Model for Gate Capacitances It turns out that the gate capacitances of an N-channel power MOSFET can be accurately modeled, in a physically correct manner, by adding a parasitic P-channel type device to the usual N-channel SPICE model. I know this seems counter-intuitive (and I've got several anecdotes about "experts" who told me I didn't know what I was talking about re this!) but please just "accept it as an assertion" for now. I'll add further explanation in the future. This concept is explained in some detail in one of my ancient papers: "An Accurate Model For Power DMOSFET's Including Interelectrode Capacitances," Scott, R. S.; Franz, G. A.; Johnson, J. L., IEEE Transactions on Power Electronics, vol. 6, no. 2, April 1991. But the SPICE model I developed way back in 1990 or so was based on an incredibly primitive SPICE MOSFET model for the parasitic PMOS device (the reason for using that highly limited SPICE model is another story which I may add in the future). Nowadays, or probably even then, I am sure I could have chosen a more modern and appropriate MOSFET model for the parasitic device that would yield MUCH, MUCH more realistic capacitances. I need to investigate this further. Quite a bit of work involved since I haven't concerned myself with MOS modeling for 20 years or so. But I am certain that using a more modern SPICE model will correct most of the inaccuracies of my old model. Please stay tuned! Update 7/3/2014 (and a little-too-much history): Well, I'm NOT SO CERTAIN NOW! For quite a while I've assumed that a more modern, but still simple, MOS Spice model would be able to fit the capacitance characteristics of a power MOSFET better than what I used back in 1990. Because it has smooth capacitance vs. voltage characteristics I thought a good candidate model would be the widely-used EKV model - but I never examined it in detail. A few weeks ago I made an effort to see if this model would indeed "do the job". There are papers on the internet that describe their capacitance formulas in detail and I looked at some. To my horror, I found that the EKV model incorporates an approximation that also plagued my 1990 model. This has to do with the voltage dependence of the bulk depletion charge capacitance, which IN THE MODEL has a dependence inversely proportional to the square root of a bias voltage term. Back then I found that I needed to slightly modify the power of this voltage term in the denominator from 0.5 (a square root) to something a bit smaller (maybe 0.4) in order to realistically fit my measured data. This was caused by a geometrical effect similar to the well-known formula for the depletion capacitance of a typical junction. The usual junction capacitance formula includes a voltage term in the denominator that is raised to a power of 0.5 or somewhat higher. The higher value adjusts the model for the geometrical effects of realistic junction curvature. The way I solved this issue in 1990 was that I called up the authors of the simulator I was using (HSPICE from MetaSoftware) and asked them to add a parameter to their simplest MOS model that would allow me to change the (fixed) power from 0.5 to a slightly lower number. These were the famous technologists Shawn and Kim Hailey. They said OK and I didn't expect to ever hear from them again. But a couple of weeks later my boss said he had received a tape in the mail with a new version of HSPICE. It included my requested model modification and I was able to continue my development. The Haileys were remarkable people. Incredibly nice and amazingly brilliant I never met either of them personally but, even though they developed the HSPICE software themselves, they still took the time to speak to and help individual engineering customers if they called. Their achievements are fascinating history. See, for example, http://silicongenesis.stanford.edu/transcripts/hailey.htm . If I wasn't certain you're already asleep by now, I'd love to relate more of the story of my ancient model! Task #3: Create a "Curve-Fit" Capacitance ModelI actually did this once, around-about 1995, as a demo for a presentation at the 1995 Saber Users Group (ASSURE) meeting. I did this using the Saber simulator. I think it took me a few weeks, mostly working at night on my own time. But those files are mostly gone, as far as I can see. So I'd have to start from scratch on this one. Still, this "old dog" has learned a few new tricks over the years regarding curve-fitting, so it should be a bit easier this time around. Plus I definitely won't have to deal with all the horrible deficits the Saber simulator had then (I'll now use something much more reliable, like LTSpice). I sort-of remember that MathCad, Excel, and Scientist all gave me the same results for my curve-fit model's capacitances, which agreed well with the device measurements. But when I transferred the exact same formulas to Saber, for some reason which I still don't understand, Saber (and ONLY Saber) gave significantly different results. And I double-checked the formulas I put into Saber many, many times. But, back then, I was pretty much used to having Saber give bogus numerical results under various conditions. I recall that I discovered this and had to investigate it and then extract new parameter values, unique to the Saber model demo, only a few days before the seminar, in order to make the Saber measured/modeled plots agree with measured data. What a pain! For a lot of reasons, and over many years, I learned to not be a big fan of Saber. Anyway, I've found several curve-fit model versions I built using Scientist and MathCad (both of which I trust). I think I have now found working original application program versions saved on my old PC that will run these model files (but the programs won't even run on my newer PC). I'm not sure which one of the formulas that I still have may be best. But I should be able to develop a curve-fit model, probably for the IRF450R data above, relatively quickly now. I intend to create an LTSpice model using these (or improved) formulas. As usual "stay tuned". But this is great news! For now, I've added a demo plot of my ancient curve fit model at this page Curve Fit Power MOSFET Capacitance Model. And you can download this simplified model in Excel form (not guaranteed to be useful as a simulator model) at Downloadable Curve Fit Power MOS Capacitance Model Formulas .
Task #4: Create a Physics-Based Capacitance ModelI also did this many years ago, but have lost almost all of the files except the very early attempts at creating this model (well, they're mostly not actually lost, just "essentially unavailable" to me). This model was largely physics-based. That is, your input to it was a lot of physical design parameters of the MOSFET such as the drain doping levels (both in the bulk epi but also including a possible surface implant), gate oxide thickness, channel length and width, etc., along with a number of "curve fitting" parameters to take care of such things as two and three dimensional effects. That model was designed to be put into the Saber simulator but the project got canceled before that happened (a long and unpleasant story). Anyway, I actually developed the model using MathCad and I still have a few old files from from the early stages of this model development (plus one xerox-ed printout of a somewhat later version). But I'll need to re-read my long, old MathCad output to explain to myself what I knew back then. Plus I'll have to "finish" it, since this wasn't the final version. Will probably take quite a bit of work, but I really need to do this in order to re-acquaint myself with the MOS theory I knew so long ago. May take many months, as it's a PHD thesis level project, but since I really need to relearn the theory anyway this might actually be the modeling method I tackle first. UPDATE 4/3/2013: Because I just found some of my old, partly-finished, "curve-fit" model formulas (see Curve Fit Power MOSFET Capacitance Model above), I may now try that type of model FIRST as a "quick gratification" effort. I still really need to "re-learn" my old MOS physics concepts though! Task #5: Measure and Model Body Diode Soft Reverse Recovery EffectsThis task has two major parts, similar to the junction capacitance model development above. Long ago I developed a power diode soft reverse recovery model enhancement to the existing abrupt-turnoff SPICE diode model (see Advanced Diode Recovery Model ). It used a very simple "subcircuit" approach, but can yield pretty good results. The same physics that describes the reverse recovery of power diffused junction diodes can also be used to describe most of the effects of reverse recovery of power MOSFET body diodes. So I don't really have any further work to do towards developing a SPICE modeling technique. This is already done. However, my old modeling techniques are entirely based on measured reverse recovery data. That is, they are curve fits to actual measured waveforms (although there are some physical arguments that can be made that indicate my subcircuit method is compatible with actual device physics). Such reverse recovery measurements require some fairly high speed measurements (often > 100 MHz bandwidth waveforms). Thus they are not particularly easy to do and require a careful test circuit design and fairly high speed test equipment (high power fast pulse generators, fairly high bandwidth scopes, and careful design of diode current measurement techniques). You digital and RF guys just shut up! I know how fast your circuits work these days, but doing (much slower) high power tests can still be challenging. I expect I won't get to this task for quite a while: tasks #1-4 above are already pretty challenging. A soft reverse recovery model is kind of "icing on the cake". But I'll eventually get to it. I may even have some old "boatanchor" equipment that is borderline-adequate for doing such measurements (see, for example, an HP 214A Pulse Generator and not-yet described HP54111D or HP 54110D boatanchor digital oscilloscopes). But such a setup will require some pretty careful design and construction, and may not be entirely capable of characterizing all modern fast recovery devices. Will have to try to see! Task #6: Extend the MOS Models to More Modern Devices (Superjunction and/or GaN and/or SiC Transistors)My old power MOSFET modeling work is based on the design of the original vertical silicon power DMOS devices. However newer designs such as silicon "superjunction", GaN, and SiC power MOSFETs have improved characteristics. For superjunction devices the physics is pretty much the same (or, at least, very similar) to the old DMOS designs. GaN and SiC devices may, or may not, operate similarly. But it would be a shame to fail to extend the models for the older-style devices, developed in tasks #1-5 above, towards creating improved models for more modern transistor types.The model formulas may need to be changed a bit to accommodate these device design changes. For example, two and three dimensional "fudge factors" for a "superjunction" MOSFET may need to be modified or further enhanced. And, for a physics-based model, the semiconductor parameters (such as bandgap, dielectric constants, etc.) will obviously need to be modified for GaN and SiC devices. In addition, if the new GaN or SiC devices are actually compound devices (I'm aware of at least one GaN product that is a MOSFET/JFET combination) modeling may be difficult or virtually impossible unless the separate devices are also available for individual characterization. This will require further investigation on my part. And, possibly, the most difficult modeling challenges may be the need to develop lower capacitance/higher switching frequency measurements for the newer devices' characterization. Particularly troublesome for me since I presently have only a VERY limited and VERY old variety of test equipment available. This "Task #6" is pretty far down my "wish list", so it's got to be a longer term goal. But I really want to at least attempt to keep up with technological changes since 1990. However, except for the device measurement/characterization implications, or the possibility of compound devices, this goal may not be quite as difficult as you might think! Please remain somewhat patient, and we'll see what happens! Copyright © 2013, 2014 Robert Steven Scott |
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