On-Chip Resonance in Nanoscale Integrated Circuits

Relentless scaling of integrated circuits has resulted in significant performance improvements. While active devices mostly benefit from scaling, passive interconnect networks have degraded in performance with scaling. Interconnect parasitic effects therefore must be considered throughout the design process. Furthermore, novel and innovative design methodologies for interconnect networks are required to maintain high performance in these highly complex integrated circuits.

The focus of this thesis is on three important interconnect networks: clock, data, and power generation and distribution networks. Design and analysis methodologies to improve the performance of these networks have been developed. Specifically, the following three topics have been addressed in this thesis.

Exploiting resonance for distributing high frequency clock signals is a promising technology to reduce power dissipation, clock skew, and jitter. A comprehensive methodology for designing these resonant networks has been developed. A case study of a 5 GHz clock signal within a resonant H-tree network has been demonstrated in a 180 nm CMOS technology, resulting in a substantial 84% reduction in power consumption as compared to a traditional H-tree network.

On-chip resonance has also been used to design a novel data distribution network. By eliminating the need for traditional buffer insertion, a significant reduction in power and latency has been observed. A methodology for designing these networks has been developed. A case study of a 5 Gbps data signal distributed within a 5 mm long interconnect has been demonstrated, exhibiting a 90% and 40% improvement in power consumption and latency, respectively, as compared to repeater insertion and several different exotic techniques.

A distributed rectifier for a buck converter implemented in three-dimensional (3-D) technology has also been developed. The proposed rectifier eliminates the need for a traditional LC filter, enabling the on-chip integration of DC-DC converters. A test circuit of the distributed rectifier has been designed for manufacture in the MIT Lincoln Laboratories 3-D 150 nm CMOS technology. Additionally, an on-chip hybrid buck converter based on switching and linear DC-DC converters has been developed, demonstrating superior efficiency and conversion range as compared to conventional buck converters.

The development of these novel design methodologies will compensate for the detrimental effects of scaling on interconnect networks. High performance operation of highly complex integrated circuits has been demonstrated to be feasible. A combination of novel design methodologies, materials, and integration technologies, are required for future nanometer integrated circuits.