In the era of rapid technology scaling, the performance and reliability of integrated circuits (IC) have reached limits that are difficult to surpass. As a result, novel design methodologies for high performance, high complexity ICs are required. Three-dimensional (3-D) nanoscale technology can provide the required characteristics of future state-of-the-art integrated systems.
With the significant performance improvement offered by 3-D circuits, new design challenges arise. One primary requirement of 3-D integrated systems is diverse, high quality, and reliable power. This fundamental issue of power generation and distribution in 3-D circuits is the focus of this research.
To reduce the performance bottleneck of on-chip interconnects in high complexity integrated circuits, advanced signaling techniques have recently been developed. Repeater insertion, the most common and widely used technique to enhance interconnect performance, can no longer satisfy the increasing demand for higher bandwidth, and lower jitter, skew, and power consumption. Advanced global data transmission networks formed in a transmitter, transmission line, and receiver topology are a promising alternative to repeater insertion.
A novel quasi-resonant interconnect networks (QRN), incorporating on-chip inductor have been developed. The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain both low power and low latency.
Most of the work on reducing the power dissipated by the clock network has focused on reducing the voltage swing, optimally inserting repeaters, clock routing, and clock gating. Clock gating has become one of the most effective and widely used techniques for mitigating power consumption. These techniques, however, cannot successfully combat the increasing demand for low skew, low jitter, low power, and high speed.
A promising technique to reducing power consumption is resonant clock distribution networks. The focus of this research is the design and analysis of resonant clock distribution networks, supporting design techniques and methodologies, where speed, area, and power dissipation tradeoffs are investigated.
The focus of this research is the design and analysis of high performance analog integrated circuits, and supporting design techniques, methodologies, and circuit structures. Bulk-driven low power OTAs, Gm-C filters, differential difference amplifiers (DDA), and column-based ADC for CMOS image pixel arrays, have been developed.
Last updated 12/27/2008