Senior Research Scientist
Intel Labs


Current Research: Spatial programming for productive performance

Programmatic Control of a Compiler for Generating High-performance Spatial Hardware

Expressing Sparse Matrix Computations for Productive Performance on Spatial Architectures

Productively Expressing High-performance Spatial Designs of Givens Rotation-based QR Decomposition Algorithm

A compiler is under construction for the above ideas. Academic collaboration is welcome.

Previous Research

Sparso: Context-driven Optimizations of Sparse Linear Algebra
Hongbo Rong, Jongsoo Park, Lingxiang Xiang, Todd Anderson, Mikhail Smelyanskiy. PACT, 2016. [PDF[Open Source]

Automating Wavefront Parallelization for Sparse Matrix Codes.
Anand Venkat, Mahdi Soltan Mohammadi, Jongsoo Park, Hongbo Rong, Rajkishore Barik, Michelle Mills Strout, Mary Hall. SC, 2016. Nominated as a Best Paper Finalist

ProductiveC: Enabling High Productivity in C-Family Languages
Hongbo Rong
Computing Frontiers (CF), 2015. [PDF

Just-in-time Software Pipelining
Hongbo Rong, Hyunchul Park, Youfeng Wu, Cheng Wang.
International Symposium on
Code Generation and Optimization (CGO), 2014. Best Paper Award. [PDF

Allocating Rotating Registers by Scheduling
Hongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu.
International Symposium on Microarchitecture (MICRO), 2013. [PDF][PPT]

Tree Register Allocation
Hongbo Rong. Symposium on Microarchitecture (MICRO), 2009. [PDF][PPT]
Single-Dimension Software Pipelining for Multi-Dimensional Loops
Hongbo Rong, Zhizhong Tang, R. Govindarajan, Alban Douillet, Guang R. Gao.
International Symposium on Code Generation and Optimization (CGO), 2004. Best Paper Award. [PDF]
ACM Transactions on Architecture and Code Optimization (TACO), 2007. [PDF]
Register Allocation for Software Pipelined Multi-dimensional Loops
Hongbo Rong, Alban Douillet, Guang R. Gao.
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2005. [PDF]
ACM Transactions on Programming Languages and Systems (TOPLAS), 2008. [PDF

Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops.
Hongbo Rong, Alban Douillet, R. Govindarajan, Guang R. Gao. International Symposium on Code Generation and Optimization ( CGO), 2004. [PDF

Book chapter

Advances in Software Pipelining.
Hongbo Rong, R. Govindarajan.
Chapter 20 in Compiler Design Handbook: Optimizations and Machine Code Generation. Srikant and Shankar Eds. 2nd Edition. 2007

Product components

Visual C++ compiler
Type system and C++ optimizations.
Phoenix compiler
Local scheduler and dependence graph.
Code quality analysis.
Warning phase.
Bartok compiler
Card marking writer barrier



Methods, systems and apparatus to optimize sparse matrix applications
Hongbo Rong, Jongsoo Park, Mikhail Smelyanskiy, Geoff Lowney. US Patent, No. 9720663

Technologies for low-level composable high performance computing libraries
Hongbo Rong, Peng Tu, Tatiana Shpeisman, Hai Liu, Todd A. Anderson, Youfeng Wu, Paul M. Petersen, Victor W. Lee, P. G. Lowney, Arch D. Robison, Cheng Wang. US Patent, No. 9690552

Allocation of alias registers in a pipelined schedule
Hongbo Rong, Cheng Wang, Hyunchul Park, Youfeng Wu. US Patent, No. 9495168

Software Pipelining at Runtime
Hongbo Rong, Hyunchul Park, Youfeng Wu. US Patent, No. 9239712

Dynamic Optimization of Pipelined Software
Hyunchu Park, Hongbo Rong, Youfeng Wu. US Patent, No. 9170792

Method and Products for Processing Loop Nests
Hongbo Rong, 
 Guang R. Gao, Alban Douillet, R. Govindarjan. US Patent, No. 7631305. 

容红波, 汤志忠. 中国专利, 2003. No. 00133535.9.

Instruction and logic to monitor loop trip count and remove loop optimizations
Jaewoong Chung, Hyunchul Park, Hongbo Rong, Cheng Wang, Youfeng Wu. US Patent. No.9715388.

Co-designed dynamic language accelerator for a processor
Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park. US Patent. No. 9542211