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ICT Verification and Validation

Foreword by the Chair

Eda Marchetti (ISTI-CNR, Italy)

ICT systems are assuming a key role in real-life and are involving more and more human judgement, political legal and social aspects, technical facilities and limitations. As a result, guaranteeing that such systems satisfy their functional and non-functional requirements becomes at the same time imperative and increasingly difficult. Challenges descend, among others, from new infrastructures, heterogeneity, openness and continuous evolution, technical and semantic interoperability barriers, security and trust concerns. In this complex scenario, the Verification and Validation (V&V) activities, evolving in parallel with software development, represent an important and fundamental mean for guaranteeing the integrity, adequacy and requirements conformance of the ICT systems.

Following the tradition of the previous editions, the QUATIC 2014 ICT Verification and Validation track has collected innovative solutions, proposals and experiences for ICT quality assurance, seamlessly integrated within the ICT lifecycle, with a progressive shift from the traditional design-time model towards a run-time on-line one.

The papers selected in this track dedicate specific attention on approaches and methods for automatic model-based V&V, that can be easily integrated in the industrial context and can reduce the gap between research and practice. Thus proposals include innovative methodologies for test case generation and simulation in specific contexts, like nuclear control and railway interlocking systems; specific model-based testing approaches for mobile applications or components of telecommunication protocols; empirical investigation about the applicability of combinatorial testing tools in company, and testing strategies and framework useful in the access control environment.

Model-based V&V approaches are valid means for increase systematization, reusability and diminish the effort in modelling and testing of ICT systems. However one issue in the V&V process is how to use or adapt available V&V proposal to specific context and situations. To this purpose four papers of this track propose interesting solutions.

In “Automatic test set generation for function block based systems using model checking” Lahtinen faces this problem considering the nuclear instrumentation and control (I&C) systems, which are designed using a function block diagram description of the system itself. The author develops a technique, implemented into a proof-of-concept tool, for generating structure-based test sets for function block based.

In “Model-based testing for Mobile Applications” Costa, Nabuco and Paiva present a study aiming to assess the feasibility of using the pattern based GUI testing approach, PBGT, to test mobile applications. Although PBGT was developed having web applications in mind, authors identify the adaptations and updates necessary to the PBGT in order to test mobile applications.

In “On testing against partial non-observable specifications” Kushik, Yevtushenko and Cavalli focus on testing software components that implement telecommunication protocols. The authors discuss about how Finite State Machines (FSMs) might be used when deriving high quality tests and which properties can be held for corresponding FSMs when increasing/decreasing an abstraction level for the protocol specification.

Finally in “Validation of Railway Interlocking Systems by Model Based Testing, a Case Study” Bonacchi and Fantechi show how costly validation processes can be reduced during the production railway interlocking systems, by extracting a model of the implemented interlocking logic from the on-target description of the topology.

In “An automated testing framework of model-driven tools for XACML policy specification” Bertolino, Daoudagh, Lonetti and Marchetti consider instead the problem of testing the facilities for model-to-code translation. The authors face the problem considering the specific access control environment and propose an integrated framework for testing the automatic translation of the specification of an access control model into an XACML policy.

Discussion about the practical limitations of the different V&V proposals in real-word context is finally considered in “Combinatorial Testing in an Industrial Environment–Analyzing the Applicability of a Tool” Condori-Fernández, Kruse, Vos, Brosse and Bagnato. In particular the authors investigate the applicability of a combinatorial testing tool in the company SOFTEAM discussing about efficiency, effectiveness and learning effort.

In summary, the QUATIC 2014 ICT Verification and Validation track accepted 4 papers and 2 works in progress covering different topics in Verification and Validation context. We are grateful to all those who submitted papers to this event and also the revising board who helped to improve the quality of the accepted papers and their selection on this track.

Eda Marchetti is a researcher at CNR-ISTI. She graduated summa cum laude in Computer Science from the University of Pisa (1997) and got a PhD from the same University (2003). Her research activity focuses on Software Testing and in particular: developing automatic methodologies for testing, defining approaches for scheduling the testing activities, implementing UML-based tools for test cases generation, and defining methodologies for test effectiveness evaluation. She has served as a reviewer for several international conferences and journals, and she has been part of the organizing and program committee of several international workshops and conferences. She has (co)authored over 50 papers in international journals and conferences.

Invited Speaker

Sasikumar Punnekkat, Innovation, Design & Engineering at Mälardalen University (MDH), Sweden

Survival in the Dynamic Landscape of Verification, Validation and Certification

Verification and validation (V&V) research has a long-standing history and has produced a large set of methods and results, many of them successfully used by the industry. However an honest introspection will reveal clear gaps as well as growing divergence between industrial practices and academic research. New development paradigms, higher complexity of systems, and increasing quality/certification requirements are keeping the V&V researcher under constant pressure for updating research results. Some of the important challenges faced by a researcher while trying to keep pace with the ever-moving targets for verification, validation and certification are discussed in this talk (based on author¹s own experiences in both industry and academia). Conscious and constant efforts in performing reality checks on the research directions and methods are essential both for the successful adaptation of the research results by the industry as well as for keeping the relevance of the research teams. A brief overview of the related research projects and efforts at the Mälardalen University are also presented.

Sasikumar Punnekkat is a Professor of dependable software engineering at the school of Innovation, Design& Engineering at Mälardalen University (MDH), Sweden. He is the leader of the Dependable Software Engineering research group and also the program director of the Master Programs in Software Engineering at MDH. He has more than 15 years of industrial experience on software development and verification as a scientist at the Indian Space research Organization. He has a lead role in multiple European and national research projects such as SafeCer, Synopsis, Contess, Euroweb and Retnet. His research interests include multiple aspects of real-time systems, software engineering, software testing, dependability, and safety certification.

Track Committee

ChairEda Marchetti, ISTI-CNR, Italy

Local Co-Organizing ChairInês Coimbra, FEUP, Portugal

Program Committee
  • Ana Cavalli, GET-INT, France
  • M.J. Escalona, University of seville, Spain
  • Angelo Gargantini, University of Bergamo, Italy
  • Sylvia Ilieva, Sofia University, Bulgaria
  • Francesca Lonetti, CNR-ISTI, Italy
  • Ioannis Parissis, Laboratoire LCIS, France
  • Sasikumar Punnekkat, Malardalen University, Sweden
  • Antonino Sabetta, SAP Research Sophia-Antipolis, France
  • Sira Vegas, Universidad Politecnica de Madrid, Spain

Call for Papers

As ICT becomes ubiquitous and our well-being depends ever more on the proper functioning of networked software-intensive systems, guaranteeing that such systems satisfy their functional and non-functional requirements becomes at the same time imperative and increasingly difficult.  Challenges descend, among others, from new infrastructures, heterogeneity, openness and continuous evolution, technical and semantic interoperability barriers, security and trust concerns, blurred distinction between developer and user.

To cope with such complex scenarios, new development approaches, paradigms and methodologies as well as automatic facilities and practical solutions are still necessary.  The aim of ICT Verification and Validation (V&V)  track is to provide innovative proposals  for ICT quality assurance,  seamlessly integrated within the ICT lifecycle, with a progressive shift from the traditional design-time model towards a run-time on-line one. 

Suggested topics of interest for this track therefore include, but are not restricted to:
  • V&V approaches in the context of SPL, MDD, AOSD, CBSE, SOA, Cloud computing...
  • V&V of non-functional requirements (reliability, performance, usability…)
  • V&V approaches for security systems (testing, risk analysis, vulnerability..)
  • Qualitative and quantitative methods to V&V
  • Formal and model-based approach to V&V
  • Off-line vs. on-line approaches to V&V
  • Automation of V&V activities
  • Empirical studies on V&V approaches and processes
  • Case studies and success stories of application of V&V research results

Paper submission

Authors should submit to a PDF version of their paper. Papers must be in CPS format and not exceed 6 pages, including figures, references, and appendices. Submissions must be original and will be reviewed by the Track Program Committee. Accepted papers will be be submitted for archiving in Xplore and CSDL, subject to one of the authors registering for the conference. The authors of the 3 best papers of this thematic track will be invited to submit extended versions to the main track of the conference. More info on the QUATIC’2014 selection process and its tracks can be found at

Important dates

Abstract submission: April 21, 2014 (optional)
Paper submission: April 28, 2014
Authors’ notification: May 26, 2014
Registration and Camera-ready: July 10, 2014 (extended to July 21, 2014)