I am Qiongzhi Wu, from Beijing China. I got my PhD. and started teaching/researching in the Beijing Institute of Technology at 2004. Since March 2015, I became a visiting scholar of the UC San Diego, in Prof. Kastner's researching team (http://kastner.ucsd.edu). 

My research area includes the signal processing, programmable logic device and high performance digital system. Actually, I am a good hardware designer and a fair FPGA programmer. In passed 10 years, I had designed many (I can't remember how many) hardware boards, including DSP, FPGA, A/D, D/A, memory and various interfaces, with a unbeaten record. Now, me and my team in China are starting up a new career which providing high-end mass-storage devices (web link is coming). 

My resent research project in UCSD is the RIFFA Builder. It's a rapid system integration tool for the RIFFA (Reusable Integration Framework for FPGA Accelerators, http://riffa.ucsd.edu). This project try to help users integrating their arithmetic design into the RIFFA architecture, producing the final FPGA RTL design and the host program, even without RTL and C/C++ coding. The first version can be find in the GitHub (https://github.com/wuqiongzhi/RIFFA_Builder).

My email address is:  qiongzhi.wu@gmail.com