PHU HA-VAN
R&D Engineer at Secure-IC, France
Ph.D. at INRIA, France
Van-Phu HA is currently a R&D engineer at Secure-IC, a company offering embedded secure elements. Van-Phu obtained PhD degree at Institut national de recherche en informatique et en automatique (INRIA). His research interests are trusted computing, designing and implementing applications in Digital Signal Processing, Image Processing and Artificial Intelligence on SoC, FPGA and ASIC platforms for energy efficiency, high performance computation and high reliability.
Contact
Email: phuhavan@gmail.com
Phone: +33 6 68 65 18 05
CV (in PDF): English version / French version
Git: github.com/phuhavan
Personal blog: phuhavan.github.io/
Education
Ph.D. candidate in Computer Science at CAIRN team, INRIA Rennes – Bretagne Atlantique, from 11.2017
Master in Integration Circuits and Systems, (GPA: 15.4/20, ranked 1st) at Centrale Supelec, Université Paris Sud and Telecom Paris-Tech
Master in Electronics Engineering, (GPA: 9.3/10) at Hanoi University of Science and Technology (HUST) in 2016
Engineer degree (5 years) in Electronic and Telecommunication, (GPA: 8.8/10, top 5% of 526 students) at Hanoi University of Science and Technology in 2014
Professional Experience
Secure-IC, R&D Engineer (7/2022-present)
INRIA, Ph.D. (11/2017 - 01/2021)
Thesis: Application-Level Tuning of Accuracy
Supervisor: Dr. Tomofumi Yuki and Prof. Olivier Sentieys
Optimize Energy-Efficiency for massive applications in IoT and mobile devices by tuning the accuracy of the applications
Develop 2 algorithms to automatically determine custom number representations and word-lengths (i.e., bit-width) for FPGAs and ASIC designs at the C source level in the context of High-Level Synthesis
Develop 2 frameworks for Datatype Exploration which is currently used by Huawei for optimizing its phone camera chips and is the basis of a start-up, created in 2020
https://gitlab.inria.fr/gecos/gecos-float2fix (written in Java)
https://gitlab.inria.fr/vaha/bayesian-opt-wlo (currently be private, written in Python with some machine learning models for hyper-parameter optimization)
Telecom ParisTech, Internship (04/2017 - 09/2017)
Study of Deep Learning algorithms under Hardware perspective
Supervisor: Prof. Lirida Naviner
Implement CNN accelerator (for MNIST dataset) on FPGA Zedboard based on Hardware/Software Co-Design Flow
HUST, Research assistant (02/2011 - 05/2016)
Supervisor: Dr. Hoang Thanh Tung, Dr. Nguyen Duc Minh and Dr. Dang Quang Hieu
Study and develop digital signal processing accelerators (CORDIC, SVD, FFT, ...) in SoC/FPGA/ASIC
Honors and Awards
Paris-Saclay scholarship for Master program, France, 2016
Silver award of LSI Design Contest in Okinawa, Japan, 2014
Second prize of Competition of Vietnam Talent Young Scientists, 2014
First prize of Student Scientific Research Symposium at HUST, Vietnam, 2014
Certificate of Merit for Excellent Undergraduate Student at HUST, Vietnam, 2014
Participation Certificate of Texas Instrument MCU Design Contest 2013 (5th of 11 teams in Vietnam North)
Technical Skills
Good knowledge in Hardware IC design, FPGA implementation, Digital signal processing and Optimization algorithms
Programming Language: C/C++ (Good), Matlab (Good), Python (Good), VHDL/Verilog (Advanced)
Hardware design tools: Xilinx/Altera tools for FPGA implementation, Synopsis/Cadence/Mentor Graphics for IC design
Others: Latex (Advanced), Unix/Linux (Advanced)
Publications
Van-Phu Ha. Contributions to the scalability of automatic precision tuning. Other [cs.OH]. Université de Rennes, 2023. English. ⟨NNT : 2023URENS007⟩. ⟨tel-04189422⟩ [pdf]
Van-Phu Ha, Olivier Sentieys. Maximizing Computing Accuracy on Resource-Constrained Architectures, IEEE/ACM Design Automation and Test in Europe (DATE), April, 2023, Antwerp, Belgium [pdf]
Van-Phu Ha, Olivier Sentieys. Leveraging Bayesian Optimization to Speed Up Automatic Precision Tuning, IEEE/ACM Design Automation and Test in Europe (DATE), Feb 2021, Grenoble, France [pdf]
Van-Phu Ha, Tomofumi Yuki, Olivier Sentieys. Towards Generic and Scalable Word-Length Optimization. IEEE/ACM Design Automation and Test in Europe (DATE), Mar 2020, Grenoble, France [pdf]
Van-Phu Ha, Tomofumi Yuki and Olivier Sentieys, Noise Budgeting in Multiple-Kernel Word-Length Optimization, in 4th Workshop on Approximate Computing (AxC 2019), Mar 2019, Florence, Italy. [pdf]
Van Phu Ha, Duc Minh Nguyen, Quang Hieu Dang, Hardware/Software Co-design of Power Level Difference Based Noise Cancellation, in Proceeding of International Conference on Advanced Technologies for Communications (ATC), 2015, pp. 616-621 [pdf]
Tran Manh Hoang, Van Phu Ha, Hoang Phuong Chi, Dang Quang Hieu, Nguyen Duc Minh , Hardware Implementation of a UWB 802.15.4a Receiver, in Journal of Science and Technology Technical Universities 2014, Np.104, pp. 36-40 [pdf]