2nd Workshop on Performance Engineering for Large Scale Graph Analytics


PELGA2016 will be held in Grenoble, collocated with Europar'16


PROGRAM 

We are looking forward to welcoming you all at the second edition of PELGA, on Monday, August 22nd, 2016 in Grenoble!

Here's the program for the day: 

 9:00 -  9:05    Meet and greet, welcome note  

 9:05 -  9:50    Keynote presentation: Dr. Ir. Alexandru Iosup, Delft University of Technology
                        "Graphalytics: from Benchmarking to Performance Engineering" (slides)
  
 9:50 - 10:10    Merijn Verstraaten, Ana Lucia Varbanescu and Cees De Laat 
                        Synthetic Graph Generation for Systematic Exploration of Graph Structural Properties - paper, slides 
10:10 - 10:30    Stijn Heldens, Ana Lucia Varbanescu, Wing Lung Ngai, Tim Hegeman and Alexandru Iosup
                        Towards the Next Generation of Large-Scale Network Archives - paper, slides 
                 
10:30 - 11:00   Coffee break 
 
11:00 - 11:30  Jonathan Sumrall, George H. L. Fletcher, Alexandra Poulovassilis, Johan Svensson, Magnus Vejlstrup, Chris Vest and Jim Webber  
                      Investigations on path indexing for graph databases - paper, slides
11:30 - 12:00  Jesun Firoz, Marcin Zalewski, Martina Barnas and Andrew Lumsdaine 
                      Improving Performance of Distributed Graph Traversals via Application-Aware Plug-in Work Scheduler - paper, slides  
12:00 - 12:30  Stefano Aldegheri, Jiři Barnat, Nicola Bombieri, Federico Busato and Milan Češka. 
                      Parametric Multi-Step Scheme for GPU-Accelerated Graph Decomposition into Strongly Connected Components - paper, slides    


Keynote of the day  
Graphalytics: from Benchmarking to Performance Engineering -- slides available here 
by Dr. Alexandru Iosup

Graphs model social networks, human knowledge, and other vital information for business, governance, and academic practice. Although both industry and academia are developing and tuning many graph-processing algorithms and platforms, the performance of graph-processing platforms has never been explored or compared in-depth. Moreover, graph processing exposes new bottlenecks in traditional HPC systems (see differences in Top500 and Graph500 rankings).

In this talk, we introduce the LDBC Graphalytics benchmark, which focuses on batch full-graph analytics.  Attendees will discuss about methods and tools for performance evaluation and optimization for graph processing platforms, and hear about our view that the performance forms a dependency triangle Platform-Algorithm-Dataset. We will present real-world experiences with commonly used systems, in particular with graph-processing platforms such as Giraph, Graphmat, OpenG, PGX.D, and PowerGraph. Moving towards performance engineering, and in particular bottleneck analysis and performance diagnosis, we further focus on Granula, a component of LDBC Graphalytics for in-depth performance analysis for graph-processing systems with various data processing models.


Speaker's bio:
Dr. Alexandru Iosup is currently a tenured Associate Professor with the Distributed Systems Group at TU Delft, the Netherlands, and a member of the Young Academy (De Jonge Akademie) of the Royal Netherlands Academy of Arts and Sciences (KNAW). He received in 2009 his Ph.D. in Computer Science from TU Delft, and was a visiting scholar at U.Dortmund, U.Wisconsin-Madison, U.Innsbruck, U.California-Berkeley, and Technion-Israel (one visit every 2-3 years). 
He was awarded the 2015 Teacher of the Year of the Netherlands prize and the 2016 Dutch ICT-Research prize for the best under-40 researcher in ICT.
His long-term research interests are in the area of computing systems, including cloud computing and big data systems, and their applications, including big science, file sharing, and online gaming. He is involved in a long-term project to build the computer systems memex, by providing open access to workload and resource operation traces from all areas of computing.

For more details, check Alexandru's pageContact Alexandru at A.Iosup@tudelft.nl or @aiosup.


PELGA Context and goals

The knowledge economy is based on data, of which graphs represent an increasing part, in advanced marketing, in social networking, in life sciences, in health and bioinformatics services, in academic networks, in hiring of professionals, etc. As a consequence, graph analytics is fast becoming a significant consumer of computing resources, due to ever larger graphs of hundreds of millions up to hundreds of billions of edges, and to increased complexity of analysis tasks. To enable existing algorithms to fit modern architectures and scale with these new requirements, there is a growing need for performance engineering. 

This workshop is a venue for specialists from both industry and academia to discuss the state of the art of graph processing systems, with a special focus on performance. Contributions focusing on graph-centric performance engineering tools and methods, workload characterization, and performance modeling are especially welcome. We also invite contributions covering surveys, performance studies, comparative analyses, new algorithms and new graph processing systems. This broad mix of ideas will stir discussion and lead to new collaborations and new ideas.

Topics

We invite both mature (regular) and work-in-progress (short) papers on topics that include, but are not limited to:

  • Systems 
    • new graph processing systems focused on high­‐performance analytics
    • performance studies of existing systems to be used for graph processing
    • comparative and/or in-depth analysis of graph processing systems 
  • Algorithms, Applications, and Architectures 
    • new high­-performance graph processing algorithms 
    • new performance-aware applications for graph processing algorithms 
    • platform-specific algorithms and their performance optimization (e.g.,GPUs, Xeon Phi, heterogeneous platforms) for graph analytics
  • Algorithms and/or architectures for large scale graph analytics 
    • partitioning methods for large-scale or otherwise challenging graphs
    • performance characterization, modeling, and engineering
    • graph models for performance tuning and/or prediction of analytics workloads
    • performance models for prediction or ranking of graph processing platforms
    • performance analysis and engineering of existing graph processing algorithms
    • tools and benchmarks for graph-centric performance engineering

Submission instructions


We invite two types of submissions:
1. Regular papers (12 pages, LNCS - latex format here
A regular paper must report on original research that has not previously appeared, and has not been concurrently submitted to a journal or conference with published proceedings. Any overlap with a published or concurrently submitted paper must be clearly indicated. A regular submission must not exceed 12 LNCS pages. 

2. Short papers (6 pages, LNCS latex format here
A short paper can be a work-in-progress paper, an experience paper, or a position paper on one of the topics of the workshop. Short papers are expected to present novel and original ideas/hypotheses in the field of performance engineering from graph analytics, game-changing practices from industry or academia, interesting applications and case-studies for other fields than computer science, as well as performance evaluations of existing tools or systems. Preliminary results are appreciated, but not mandatory. 


Submission link
To submit a paper to PELGA, please use the general submission link for the EuroPar'16 - workshops page:
Please make sure you select PELGA from the list of workshops! 

Important Dates


Submission deadline: May 25, 2016 

Author notification: June 17, 2016 

Workshop paper (informal) : July 15, 2016

Workshop date: August 22 or 23, 2016 

Camera-ready deadline:  September 30, 2016 (EuroPar workshops are printed in a joined LNCS post-proceedings volume).


Organizers

Ana Lucia Varbanescu, University of Amsterdam

Program Committee

Alexandru Iosup, Delft University of Technology, The Netherlands
Arnau Prat-Perez, UPC, Spain 
Holger Fröning, University of Heidelberg, Germany 
Hannes Muhleisen, CWI, Amsterdam, The Netherlands
*Sungpack Hong, Oracle Labs, USA
*Thomas Manhardt, Oracle Labs, USA 
Jan Hidders, Vrije Universiteit Brussel, Belgium
Josep Lluis Larriba Pey, UPC, Spain 
Mihai Capota, Intel, USA 
Ted Willke, Intel, USA
Taro Takaguchi, NII Tokyo, Japan 
George Fletcher, Eindhoven University of Technology, The Netherlands
Yuechao Pan, UC Davis, USA
--
* - pending confirmation.

Subpages (2): History Keynote PELGA'16