Work Experience

Software Engineer, Atrenta R&D (July 2010 - Present)
Team: Lowpower Design Verification


Low Power Verification Challenge

Architectural design bugs that violate the principles of low power design may exist even at RTL. Such bugs are best detected early on with static checks.

Low power design techniques add new design elements at different stages of the design flow. A Power Gated design includes power switches to turn off power domains and isolation cells to protect unknown values being driven from a powered down domain that communicates with a powered up domain. Isolation cells are typically synthesized automatically. Power switches are added by a place-androute tool. Insertion and connection of the power switches and isolation cells can be validated by structural static low power rule checks. If a low power design uses Retention to save and quickly restore the contents of a powered down domain, retention register connections need to be validated after synthesis and again after place and route. Multi-voltage designs or designs using Dynamic Voltage Scaling (DVS) have different power domains operating at different voltage values. Level shifters are automatically synthesized to convert voltages of signals traversing such domains, and level shifter insertion and connectivity must be validated throughout the design flow.

For multi-voltage designs, it is important to verify that the appropriate power and ground pins are connected to the specified supply rail. This can also be accomplished by static low power rule checks on a power and ground (PG) connected netlist.

Spyglass Lowpower Policy Overview

Spyglass Lowpower Policy is a multi-voltage, static low power rule checker that allows engineers to rapidly verify the designs that use voltage control techniques for power management. It also helps to pipe-clean the power intent [IEEE 1801 Unified Power Format (UPF)] before starting implementation of the low power design. Our tool supports UPF, CPF and SGDC formats of specifying power intent.

My Contribution

Currently, I am working on an algorithm to verify the isolation strategy specifications in UPF. The role includes

-  Understanding the design scenario and intent of a UPF file

- Coming up and implementing an algorithm to verify if the intent specified yields a clean design

- Have shown steep growth in entering an absolutely unfamiliar domain and already working on the core algorithm for isolation strategy verification.

- Writing white papers and implementing Proof of Concepts (POCs)