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EOMA68-GR8

The Next Thing Co. GR8 system on module looks like a candidate for making an EOMA68 compliant compute module with slightly less pain. 
It's specs are nothing to write home about, current distros for it use binary blobs and the flashing tools are weird. 

But it costs 6usd/pcs in any volume, documentation is partially available, it's supported by mainline linux and sunxi. 
Best of all, the RAM is mounted on the module, so NO FRIGGING DDR ROUTING! 
While OSD355X series of system-on-module, or more like beaglebone-on-module chips are VERY interesting, offer more peripherals like ethernet and have larger BGA pitch, they cost MUCH more. 
So while GR8 putts more work in to escape routing the BGA chip and makes soldering it harder for a hobbyist shop like me, the cheap price and low power consumption make it more attractive. At 6usd/pop I can fuck up the soldering a few times and not break the bank. 
With the RAM on the SoM I'm hoping to get away with a cheap 4-layer 0.8mm pcb from the usual Chinese hobbyist-grade pcb vendors. 
The hardest part is going to be via's as they don't do buried vias and even the via's the do are quite large. 

The current version of the EOMA68 standard is still in flux and not frozen, so at most this design can be considered "EOMA68 Compatible", despite the name as no certification authority currently exists for EOMA68 and manufacturers are prevented from self-certifying. 
So "Draft-EOMA68 Compatible" is the most I'll officially say. 

My current plan is honestly to copy as much as possible from the C.H.I.P Pro module from NTC as possible for this.
I'm no linux guru and having existing:
-Distros
-Flashing tools
-Dev board (C.H.I.P Pro devkit)
-Community, even if for the C.H.I.P modules instead of my card. 
-Open source reference design (C.H.I.P Pro)
Helps a lot. 

GR8 specs:
Allwinner R8 ARMv7 Cortex-A8 running at 1 GHz
MALI-400 GPU (yuck)
256 MB of DDR3 SDRAM
TWI (I2C) for the EEPROM
Four UARTS
Two SPI (SD cards support is hacked onto this)
two PWM outputs
a single 6-bit ADC
I2S audio
S/PDIF
one USB 2.0 Host and one USB 2.0 OTG
TTL/RGB LCD interface!
And other stuff, read the datasheet. 

For me the TTL/RGB interface is the thing that makes this project possible in my mind. 

EOMA68 Standard requires the minimum of these interfaces to be available:

18-pin RGB/TTL (for LCD Panels and DVI/VGA/HDMI or other display conversion ICs)
I2C (freely available for use except for one address: 0x51 which is reserved)
1st USB port (Low Speed, Full Speed, optionally Hi Speed/480 Mbit/s and optionally USB3.0 or USB3.1)
2nd USB port (Low Speed, Full Speed, optionally Hi Speed/480 Mbit/s)
SD/MMC 4-bit wide with multiplexing to SD/MMC and SPI on 6 pins
4 pins "External Interrupt" capable GPIO that are guaranteed to generate a fast hardware interrupt to the SoC
1 pin "PWM" which is also multiplexed to GPIO
SD/MMC (and down-level compatibility to SPI) multiplexed with 6 of the GPIO pins.
TTL-compatible UART (Tx and Rx only) also multiplexed to GPIO
SPI up to 4-bit wide, multiplexed with 6 GPIO pins

The GR8 SoM should have all of these available, and more. 
All the GPIO and apparently other interfaces on the 68pin connector require tri-State buffers according to the EOMA68 standard.
This adds a shitload of annoying stuff to do. Especially as these need to be High-Z on boot. 
But thankfully most of the GPIO on GR8 is High-Z on reset.
Additional problem is that EOMA68 wants TWO USB2.0 ports on the 68pin connector. 
This would take both of the usb controllers available on GR8. 
Without a front panel power port (like USB-OTG ) the compute module cannot be powered as-is and thus is not EOMA68 compatible. 
So I'll have to include some USB HUB chip on the module, If I want USB on the front panel. 
It's likely going to be TUSB2046 or something similar from TI as those are state machines without any firmware. 
If everything goes well I can feed it 6MHz or 48MHz clock from the GR8 SoC instead of a separate SMD crystal.
This would give me one USB OTG port with dedicated hardware. 
Two USB 2.0 ports on the 68pin connector and two "spare" ports inside. 
The spare ports could be routed to the front or used for some USB integrated USB peripherals. 
TUSB2046 might also need a separate power switch IC for the USB ports, for example TPS2044, but if none of the ports expose power wiring to the world, it can be omitted. So power switching is only needed if the "spare" ports are routed to the front of the case.

I'm also interested in embedding some NAND flash on the board. Likely on the backside of it has non-bga flash chips are still somewhat solderable by hand. 
But skipping the NAND and using eMMC or an additional front-accessible SD card slot is a better idea. And cheaper. 
Possibly the exact same Toshiba chip as used by NTC on C.H.I.P Pro or something compatible. 
 
No internal wifi on the compute module for my design. If I can fit it, maybe a CC1101 or SI4464 Sub-GHz transceiver to mix things up a bit. 
There's plenty of I2C to go around, same for SPI. The fanout decides this too, along with available front panel space for antenna connector and pcb real estate. 

On the front side opposite to the 68pin connector I'm hoping to include these interfaces available on the GR8 SoM:

USB-OTG via micro-usb connector (while USB-C would be nice, I'm unsure if AXP209 supports it and micro-usb is still nice and available).
MicroSD card slot for additional storage. aka the second SD card interface on GR8.
CVBS TV out, via a 2.54mm or 1.27mm 2pin or 3pin pinheader as it's the only video interface in addition to the TTL/RGB
Sound, either via a single 3.5mm TRRS jack or separate mic/line-in and line out 3.5mm TRS jacks if space permits. 
If space and fanout permits, additional audio on TRRS or pinheader. TRRS is hard as one needs to source those "half in the middle of the board"-style of connectors for it and that's hard. 
Hardware buffered 3.3v or 5V ESD protected serial port, with hardware flow control if possible. 
On a 2.54mm or 1.27mm pinheader. If any of that is included, it's likely on a 90* 1.27mm pinheader or some slim multipin connector with it's own breakout cable. 

All this as far as BGA fanout permits, this is the real limiting factor in this design. The original C.H.I.P Pro PCB is 6layers and I'd really prefer 4layers, but that could easily mean major re-design of stuff. 
Microvia's and 6layers would make the BGA fanout quite simple, as I could jsut re-use the C.H.I.P Pro stuff with minimal mods. 

EOMA68 pinout vs. GR8 pinout:
 EOMA68 pin description    GR8 pin description Other
 1 GPIO(12) SPI_MISO(SPI_IO1)  PC1 SPI0-MISO 
 2 LCD Pixel Data bit 18 (Blue2)  PD18 LCD-D18 
 3     LCD Pixel Data bit 20 (Blue4) PD20 LCD-D20 
 4 LCD Pixel Data bit 22 (Blue6) PD22     LCD-D22 
 5 GPIO (14) / SPI_CLK PC2 SPI0-CLK 
 6 LCD Pixel Data bit 10 (Green2) PD10 LCD-D10 
 7 LCD Pixel Data bit 12 (Green4) PD12 LCD-D12 
 8 LCD Pixel Data bit 14 (Green6) PD14 LCD-D14 
 9 GPIO (16) EINT1   External interrupt1
 10 LCD Pixel Data bit 2 (Red2) PD2 LCD-D2 Shared pin with UART2-TX
 11 LCD Pixel Data bit 4 (Red4) PD4 LCD-D4 Shared pin with UART2-CTS
 12 LCD Pixel Data bit 6 (Red6) PD6 LCD-D6 
 13 LCD Pixel Clock PD24 LCD-CLK 
 14 LCD Horizontal Synchronization PD26 LCD-HSYNC 
 15 I2C Clock (SCK) PB15 TWI1-SCK I2C SCK for the config EEPROM
 16 GPIO (0) /SDMMC-D3 PF4 SDC0-D3 
 17 GPIO (2) /SPI_IO2 NC SPI-IO2???? 
 18 GPIO (4) /SDMMC-CMD PF3 SDC0-CMD 
 19 GPIO (6) /SDMMC-D0 PF1 SDC0-D0 
 20 GPIO (18) EINT3   Externall interrupt3
 21 GPIO (20)    
 22 GPIO (10) /PWM PB2 PWM0 The mandatory PWM channel
 23 GPIO (8) /UART_TX PE10 UART1-TX Shared with CSI-D6
 24 PWR (5.0V)  Connected to PMIC 
 25 not used /USB3 StdA_SSRX- NC  
 26 not used /USB3 StdA_SSTX- NC  
 27 not used /USB3 StdB_SSRX- NC  
 28 not used /USB3 StdB_SSTX NC  
 29 PWR (5.0V) NC Connected to power plane 
 30 1st USB2 (Data+)   
 31 GND GND Ground plane 
 32 GPIO (11) /EINT0   
 33 GND         GND Ground plane   
 34 2nd USB2 (Data+)   
 35 GPIO (13) /SPI_MOSI(SPI_IO0) PC0         SPI0-MOSI 
 36 LCD Pixel Data bit 19 (Blue3) PD19 LCD-D19 
 37 LCD Pixel Data bit 21 (Blue5) PD21     LCD-D21 
 38 LCD Pixel Data bit 23 (Blue7) PD23 LCD-D23 
 39 GPIO (15) /SPI_CS PC3 SPI0-CS0 
 40 LCD Pixel Data bit 11 (Green3) PD11 LCD-D11  
 41 LCD Pixel Data bit 13 (Green5) PD13 LCD-D13 
 42 LCD Pixel Data bit 15 (Green7) PD15 LCD-D15 
 43 POWER#   
 44 LCD Pixel Data bit 3 (Red3) PD3 LCD-D3 Shared pin with UART2-RX
 45 LCD Pixel Data bit 5 (Red5) PD5 LCD-D5 Shared pin with UART2-RTS
 46 LCD Pixel Data bit 7 (Red7) PD7 LCD-D7 
 47 LCD Vertical Synchronization PD27         LCD-VSYNC 
 48 LCD Pixel data enable (TFT)  PD15     LCD-DE
 49 I2C Data (SDA) PB16 TWI1-SDA I2C SDA for the config EEPROM
 50 GPIO (1) /SDMMC-D2 PF5 SDC0-D2 
 51 GPIO (3) /SPI_IO3 NC SPI-IO3??? 
 52 GPIO (5) /SDMMC-CLK PF2 SDC0-CLK 
 53 GPIO (7) /SDMMC-D1 PF0 SDC0-D1 
 54 GPIO (19)   
 55 GPIO (21)   
 56 GPIO (17) /EINT2   External Interrup2
 57 GPIO (9) /UART_RX PE11 UART1-RX Shared with CSI-D7
 58 PWR (5.0V)      Connected to power plane 
 59 not used /USB3 StdA_SSRX+ NC  
 60 not used /USB3 StdA_SSTX+ NC  
 61 not used /USB3 StdB_SSRX+ NC  
 62 not used /USB3 StdB_SSTX+ NC  
 63 PWR (5.0V)  Connected to power plane 
 64 1st USB2 (Data-)  From HUB 
 65 GND             GND Ground plane 
 66 VREF-TTL (GPIO TTL Voltage ref)
  Connected to whatever is the GR8 gpio voltage
 67 GND         GND Ground plane 
 68 2nd USB2 (Data-)  From HUB 

As C.H.I.P Pro uses AXP209 PMIC, this card will do so as well, even if the single cell lithium charging capability is more or less completely wasted. 
Existing code, drivers and schematics are the deciding factor. AXP209 consumes one I2C interface (TWI0) as I don't want anything else on that I2C bus. 

TWI0 is not shared, which is good for AXP209 control. 
TWI1 is not shared. 
TWI2 is not shared. 

So we get 4x 0.5A from the four powerpins on the 68pin connector. This sets the absolute maximum powerdrain the card can pull. 
Thus if we feature extra USB ports with 5V lines on the outside of the card, we need to include overcurrent protection. 
I'm yet to decide if the power plane on the design will be 5V or 3.3V. Most likely it's going to be 3.3V, like on the C.H.I.P Pro.

The SPI interface is just MOSI/MISO/CLK/CE, no extra bits. as the standard says "SPI up to 4-bit wide, multiplexed with 6 GPIO pins", I'm using the normal SPI interface and leaving the rest unconnected. 

SPI0 shares pins with NWE/NALE/NCLE/NCE1 flash stuff. 
SPI1 shares pins with UART1.
SPI2 shares pins with CSI interface and JTAG.


There's 3pcs SD interfaces in the GR8, if fanout allows, it would be neat to put some low profile internal mircoSDcard slot or serialNAND on the card. 
SDC0 shares pins with JTAG and UART0. This would offer awesome, if non-standard debugging on the EOMA68 68pin connector. 
SDC1 shares pins with UART1, which I was planing on using for the connector serial port, as UART0 shares pins with the RGB/TTL interface. 
SDC2 shares pins with the CSI camera interface, which is not used in EOMA68 and the NDQ stuff, it appears on TWO sets of pins in the datasheet. 


UART0 shares pins with SDC1.
UART1 shares pins with the CSI interface.
UART2 shares pins with the LCD interface. 
UART3 is free of multiplexed functionality outside of external interrupts. 

So if I put SPI2 and SDC0 to the connector, I'll also gain a JTAG port there, which would be nice for manufacturing testing. 

As for licensing the design its tbd, some nice and permissive license like BSD, MIT, TAPR or if significantly based on the original C.H.I.P Pro design, then CC BY-SA 3.0 US
I wonder if I should reserve an EOMA68 MIC code for me.

Some links on the subject:
EOMA68 standard:

EOMA68 hardware standard:

GR8 datasheet:

C.H.I.P Pro github repository:

My fork of the official C.H.I.P Repository, it contains my mods and other work:
I converted the original OrCAD files in to an Altium.PrjPcb and fixed most some of the errors. 
Unfortunately I don't have a license for Allegro nor do I have it installed, so I cannot import the binary format .brd files in to Altium.

When I have a better version of my EOMA68-GR8 compute card I'll make a public github repository for it.
The overall aim is to release ALL the required manufacturing files for it. Including fixtures, software and instructions for flashing and production testing the units.  

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