Publication

論文著述

(A)    期刊論文

1.          Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, “Improved High Code-Rate Soft BCH Decoder Architectures with One Extra Error Compensation,” has been accepted by IEEE Trans. VLSI Syst.

2.          Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, and Chen-Yi Lee, “A 5.79Gbps Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications,” IEEE J. Solid-State Circuits, vol.47, no.9, pp.2246 -2257 , September 2012.SCI/EE

3.          Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, and Chen-Yi Lee, “An Efficient DPA Countermeasure with Randomized Montgomery Operations for DF-ECC Processor,” IEEE Trans. Circuits Syst. II, vol.59, no.5, pp.287-291, May 2012SCI/EE

4.          Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, and Chen-Yi Lee, “A 2.37Gb/s 284.8mW Rate-Compatible (491,3,6) LDPC-CC Decoder,” IEEE J. Solid-State Circuits., vol.47, no.4, pp817-831, April 2012.Invited, SCI/EE

5.          Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, “A True Random Based Differential Power Analysis Countermeasure Circuit for AES Engine,” IEEE Trans. Circuits Syst. II., vol.59, no.2, pp.103-107, February 2012.SCI/EE

6.          Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, and Chen-Yi Lee, “A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memories,” IEEE Trans. Circuits Syst. II, vol.58, no.10, pp.682-686, October 2011.SCI/EE

7.          Cheng-Chi Wong and Hsie-Chia Chang, “High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver,” IEEE Trans. Circuits Syst. I, vol.58, no.6, pp.1412-1420, June 2011.SCI/EE

8.          Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, and Wei Hwang, “A Low Power Differential Cascade Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder, “J. Low Power Electronics, vol.6, no.4, pp.551-562, December 2010.EI

9.          Yi-Ming Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “A 26.9K 314.5Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 System,” IEEE J. Solid-State Circuits, vol.45, no.11, pp.2330-2340, November 2010.Invited, SCI/EE

10.       Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, “A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators,” IEEE Trans. Circuits Syst. II, vol.57, no.7, pp.546-550, July 2010.SCI/EE

11.       Cheng-Chi Wong and Hsie-Chia Chang, “Reconfigurable Turbo Decoder with Parallel Architecture for 3GPP LTE System,” IEEE Trans. Circuits Syst. II, vol.57, no.7, pp.566-570, July 2010.SCI/EE

12.       Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, and Chen-Yi Lee, “Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 422~432, February 2010.SCI/EE

13.       Chih-Hao Liu, Chien-Ching Lin, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu and Shyh-Jye Jou, “Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network,” IEEE Trans. Circuits Syst. II, vol.56, no.9, pp.734-738, September 2009.SCI/EE

14.       Hsie-Chia Chang, Chien-Ching Lin, Fu-Ku Chang, and Chen-Yi Lee, “A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders,” IEEE Trans. Circuits Syst. I, vol.56, no.9, pp.1960-1967, September 2009.SCI/EE

15.       Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, and Shyh-Jye Jou, “An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 684~694, March 2008.SCI/EE

16.       Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, and Chih-Wei Liu, “Self-Compensation Technique for Simplified BP Algorithm,” IEEE Trans. Signal Processing, vol. 55, no. 6, pp. 3061~3072, June 2007.SCI/EE

17.       Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, “A Low Power Turbo/Viterbi Decoder for 3GPP2 Applications,” IEEE Trans. VLSI Syst., vol. 14, no. 4, pp.426-430, April 2006.SCI/EE

18.       Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, “Design of a Power-Reduction Viterbi Decoder for WLAN Applications,” IEEE Trans. Circuits Syst. I. vol.52, no.6, pp. 1148~1156, June 2005.SCI/EE

19.       Hsie-Chia Chang, Chien-Ching Lin, and Chen-Yi Lee, “A low-power design for the Reed-Solomon decoder,” Journal of Circuits, Systems, and Computers (JCSC), vol. 12, no. 2, pp.159-170, April 2003.SCI/EE

20.       Hsie-Chia Chang, C. Bernard Shung, and Chen-Yi Lee, “A RS-PC decoder chip for DVD applications,” IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 229~238, February 2001.SCI/EE

21.       Hsie-Chia Chang and C. Bernard Shung, “New serial architecture for the Berlekamp-Masssey algorithm,” IEEE Trans. Commun., vol. 47, no. 4, pp. 481~483, April 1999.SCI/TELECOM, EE

(B)     研討會論文

1.  Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, and Hsie-Chia Chang, “A 45nm 6bit/cell Charge-Trapping Flash Memory using LDPC-based ECC and Drift-Immune Soft Sensing Engine,” has been accepted by IEEE Int. Solid-State Circuits Conf. (ISSCC), 2013.

2.  Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, and Chen-Yi Lee, “A 3.40ms/GF(p) and 2.77ms/GF(2m) 521-Bit DF-ECC Processor With Side-Channel Attack Resistance,” has been accepted by IEEE Int. Solid-State Circuits Conf. (ISSCC), 2013.

3.  Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “First (50,2,4) Nonbinary LDPC Convolutional Code Decoder Chip over GF(256) in 90nm CMOS,” has been accepted by IEEE Asian Solid-State Circuits Conference (A-SSCC), 2012.

4.  Chen-Yang Lin, Cheng-Chi Wong, and Hsie-Chia Chang, “A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis,” has been accepted by IEEE Asian Solid-State Circuits Conference (A-SSCC), 2012.

5.  Hung-Yuan Tsai, Chi-Heng Yang, and Hsie-Chia Chang, “An Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD Applications,“ has been accepted by IEEE Asian Solid-State Circuits Conference (A-SSCC), 2012.

6.  Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, and Chen-Yi Lee, “An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor,” in Workshop on Cryptographic Hardware and Embedded Systems (CHES), Lueven, Belgium, September 2012, pp.548-564.

7.  Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “Stochastic Decoding for LDPC Convolutional Codes,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 2012, pp.2621-2624.

8.  Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, and Chen-Yi Lee, “A High-Performance Elliptic Curve Cryptographic Processor Over GF(P) with SPA Resistance,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 2012, pp.1456-1459.

9.  Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, “A Low Cost DPA-Resistant 8-bit AES Core Based on Ring Oscillators,” in Int. Symposium on VLSI Design, automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2012.

10.       Yi-Hsun Chen, Chi-Heng Yang, and Hsie-Chia Chang, “A Fully-Parallel Step-by-Step BCH Decoder over Composite Field for NOR Flash Memories,” in Int. Symposium on VLSI Design, automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2012.

11.       Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, and Hsie-Chia Chang, “A Fully Parallel BCH Codec with Double Error Correcting Capability for NOR Flash Applications,” in IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), Kyoto, Japan, March 2012, pp.1605-1608.

12.       Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang, and Michael Wang, “FPGA-Based Simulation Platform of QC-LDPC codes for NAND Flash Memory,” in Non-Volatile Memories Workshop (NVMW), San Diego, California, March 2012.

13.       Chen-Yang Lin and Hsie-Chia Chang, "A Turbo Source Coding Scheme with Low Encoding Latency for ECG Lossless Compression", in Symposium on Engineering Medicine and Biology Applications (SEMBA), Taichung, February 2012.

14.       Yi-Min Lin, Yu-Chun Huang, Chi-Heng Yang, and Hsie-Chia Chang, “A 30K 2.5Gb/s Decision-Eased Soft RS (224, 216) Decoder for Wireless Systems,” in IEEE International Symposium on Integrated Circuits (ISIC), Singapore, December 2011, pp.174-177.

15.       Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, and Chen-Yi Lee, “A 2.97 Gb/s DPA-Resistant AES Engine with Self-Generated Random Sequence,” in European Solid-State Circuits Conf. (ESSCIRC), Helsinki, Finland, September 2011, pp.71-74.

16.       Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, “A 2.56 Gb/s RS (255,239) Decoder Chip for Optical Communication Systems,” in European Solid-State Circuits Conf. (ESSCIRC), Helsinki, Finland, September 2011, pp.79-82.

17.       Yu-Hsiang Lin, Xin-Ru Lee, Chih-Lung Chen, and Hsie-Chia Chang, "Stochastic LDPC Decoder Design for IEEE 802.15.3c Standard," in VLSI Design/CAD, Taiwan, July 2011.

18.       Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, and Chen-Yi Lee, “A 2.37Gb/s 284.8mW Rate-Compatible (491,3,6) LDPC-CC Decoder,” in IEEE Symposium on VLSI Circuits, Kyoto, Japan, June 2011, pp.134-135.

19.       Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, “A Dual-Field Elliptic Curve Cryptographic Processor with a Radix-4 Unified Division Unit,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Brazil, May 2011, pp.713-716.

20.       Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang, and Michael Wang, “Two-bit Non-Uniform Quantized LDPC Codes for NAND Flash Memory,” in Non-Volatile Memories Workshop (NVMW), San Diego, California, March 2011.

21.       Xin-Ru Lee, Hsie-Chia Chang, and Chen-Yi Lee, “A Low-Power Radix-4 Viterbi Decoder Based on DCVSPG Pulsed Latch with Sharing Technique,” in IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Malaysia, December 2010, pp.1203-1206.

22.       Shiang-Yu Hung, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, and Chen-Yi Lee, “A 5.7Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802.15.3c Applications,” in IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, November 2010.

23.       Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Yao-Jen Liu, Hsie-Chia Chang, and Chen-Yi Lee, “A 521-Bit Dual-Field Elliptic Curve Cryptographic Processor with Power-Analysis Resistance “, in European Solid-State Circuits Conf. (ESSCIRC), Seville, Spain, September 2010, pp.206-209.

24.       Yen-Chin Liao, Hsiu-Chi Chang, and Hsie-Chia Chang, “Augmented-list Sphere Decoder for Coded MIMO Systems,” in VLSI Design/CAD, Taiwan, July 2010.

25.       Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, “An Improved Soft BCH Decoder with One Extra Error Compensation,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Paris, France, May 2010, pp.3941-3944.

26.       Chen-Yang Lin, Cheng-Chi Wong, and Hsie-Chia Chang, “A Multiple Code-rate Turbo Decoder Based on Reciprocal Dual Trellis Architecture,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Paris, France, May 2010, pp.1496-1499.

27.       Yi-Min Lin, Jau-Yet Wu, Chien-Ching Lin, and Hsie-Chia Chang, “A Long Block Length BCH Decoder for DVB-S2 Application,” in IEEE International Symposium on Integrated Circuits (ISIC), Singapore, December 2009, pp.171-174.

28.       Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “A 26.9K 314.5Mbps Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System,” in IEEE Asian Solid-State Circuits Conference (A-SSCC), Hsinchu, Taiwan, November 2009, pp.373-376.

29.       Shao-Wei Yen, Ming-Chih Hu, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, and Chen-Yi Lee, “A 0.92mm2 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application,” in IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, October 2009, pp.191-194.

30.       Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, and Chen-Yi Lee, “A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction,” in European Solid-State Circuits Conf. (ESSCIRC), Athens, Greece, September 2009.

31.       Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, “A 1.69Gb/s Area-Efficient AES Crypto Core with Compact On-the-fly Key Expansion Unit,” in European Solid-State Circuits Conf. (ESSCIRC), Athens, Greece, September 2009.

32.       Yi-Min Lin, Jimmy J.M Liao, Yen-Chin Liao, and Hsie-Chia Chang, “Projection-Based Decoding of Turbo Product Codes,” in VLSI Design/CAD, Taiwan, July 2009.

33.       Cheng-Chi Wong, Yung-Yu Lee, and Hsie-Chia Chang, “A 188-size 2.1mm2 Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System,“ in IEEE Symposium on VLSI Circuits, Kyoto, Japan, June 2009, pp.288-289.

34.       Yi Hsuan Wu, Yu Ting Liu, Hsiu-Chi Chang, Yen-Chin Liao, and Hsie-Chia Chang, “Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints,” in  IEEE Int. Conf. on Communications (ICC), Beijing, China, May 2008, pp.4496-4500.

35.       Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, and Yar-Sun Hsu, “Multi-mode Message Passing Switch Networks Applied for QC-LDPC Decoder,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Seattle, U.S., May 2008, pp.752-755.

36.       Yi-Kai Lin, Chih-Lung Chen, Yen-Chin Liao, and Hsie-Chia Chang, “Structured LDPC Codes with Low Error Floor Based on Peg Tanner Graphs,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Seattle, U.S., May 2008, pp.1846-1849.

37.       Hsiu-Chi Chang, Yen-Chin Liao, and Hsie-Chia Chang, “Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems,” in IEEE Workshop on Signal Processing Systems (SIPS), Shanghai, China, October 2007, pp.45-49.

38.       Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, and Yu-T. Su, “A 0.22nJ/b/iter 0.13µm Turbo Decoder Chip Using Inter-Block Permutation Interleaver,” in IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, October 2007, pp.273-276.

39.       Yun-Lu Chen, Chih-Yeh Tseng, and Hsie-Chia Chang, “Design and Implementation of Reconfigurable RSA Cryptosystem,” in Int. Symposium on VLSI Design, automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2007, pp.252~255.

40.       Dah-Jia Lin, Chien-Ching Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length,” in Int. Symposium on VLSI Design, automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2007, pp.99~102.

41.       Cheng-Hao Tang, Cheng-Chi Wong, Chih-Lung Chen, Chien-Ching Lin, and Hsie-Chia Chang, “A 952MS/s Max-Log MAP Decoder Chip using Radix-4×4 ACS Architecture,” in IEEE Asian Solid-State Circuits Conference (A-SSCC), Hangzhou, China, November 2006, pp.79~82.

42.       Yen-Chin Liao, Hsie-Chia Chang, and Chih-Wei Liu, “Carry Estimation for Two’s Complement Fixed-Width Multipliers,” in IEEE Workshop on Signal Processing Systems (SIPS), October 2006, pp.345~350.

43.       Hong-An Huang, Yen-Chin Liao, and Hsie-Chia Chang, “A Self-Compensation Fixed-Width Booth Multiplier and Its 128-point FFT Applications,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Kos, Greece, May 2006, pp.3538~3541.

44.       Fuh-Ke Chang, Chien-Ching Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A Universal Architecture for Reed-Solomon Error-and-Erasure Decoder," in IEEE Asian Solid-State Circuits Conference (A-SSCC), Hsinchu, Taiwan, November 2005, pp.229~232.

45.       Tien-Yuan Hsiao, Chien-Ching Lin, and Hsie-Chia Chang, “An AS-DSP for FEC Applications,” in IEEE Workshop on Signal Processing Systems (SIPS), Athens, Greece, November 2005, pp.609~612.

46.       Yen-Chin Liao, Chien-Ching Lin, Chih-Wei Liu, and Hsie-Chia Chang, “A Dynamic Normalization Technique for Decoding LDPC Codes,” in IEEE Workshop on Signal Processing Systems (SIPS), Athens, Greece, November 2005, pp.768~772.

47.       Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, and Chen-Yi Lee, “A 3.33Gb/s (1200,720) Low-Density Parity Check Code Decoder,” in 31th European Solid-State Circuits Conf. (ESSCIRC), Grenoble, France, September 2005, pp.211~214.

48.       Fuh-ke Chang, Wei-Chun Hsu, Chien-Ching Lin, and Hsie-Chia Chang, “Design and implementation of a reconfigurable architecture for (528,518) Reed-Solomon Codec IP,” in IEEE 3rd Northeast Workshop on Circuits and Systems (NEWCAS), Quebec, Canada, June 2005, pp.87-90.

49.       Yuan-Mao Chang, Cheng-Wei Kuang, Chien-Ching Lin, Tzu-Shien Sang, Hsie-Chia Chang, and Chen-Yi Lee, “A new channel equalizer for OFDM-based wireless communications,” in Int. Symposium on VLSI Design, automation and Test (VLSI-DAT), Hsinchu, Taiwan, June 2005, pp.104~107.

50.       Hsuan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “A 480 Mb/s LDPC-COFDM-based UWB Baseband Transceiver,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, February 2005, pp. 444~445.

51.       Chien-Ching Lin, Fuh-Ke Chang, Hsie-Chia Chang, and Chen-Yi Lee, “An universal VLSI architecture for bit-parallel computation in GF(2m),” in IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Tainan, Taiwan, December 2004, pp.125-128.

52.       Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, “A dual mode channel decoder for 3GPP2 Mobile Wireless Communications,” in 30th European Solid-State Circuits Conf. (ESSCIRC), Leuven, Belgium, September 2004, pp.483~486.

53.       Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, and et al., “Multi-level memory systems using error control codes,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 2004, vol. 2, pp.393~396.

54.       Yi-Chen Tseng, chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, “A power and area efficient multi-mode FEC processor,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 2004, vol. 2, pp.253~256.

55.       Chao-Long Tsai, Hsueh-Kun Liao, Hsie-Chia Chang, and et al., “A CMOS SoC for 56/32/56/16 COMBO Driver Applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, February 2004, pp.428~429.

56.       Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, and Chen-Yi Lee, “A 300MHz Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm,” in 28th European Solid-State Circuits Conf. (ESSCIRC), Florence, Italy, September 2002, pp.519~522.

57.       Hsie-Chia Chang, Chien-Ching Lin, and Chen-Yi Lee, “A low-power Reed-Solomon decoder for STM-16 optical communications,” in IEEE ASIA Pacific Conf. on ASICs (AP-ASIC), Taipei, Taiwan, August 2002, pp. 351~354.

58.       Hsie-Chia Chang, and Chen-Yi Lee, “An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm,” in IEEE Int. Symposium on Circuits and Systems (ISCAS), Sydney, Australia, May 2001, vol. 2, pp. 649~652.

59.       Hsie-Chia Chang, C.Y. Cheng, S.H. Tsai, and Chen-Yi Lee, “A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm,” in IEEE 43rd Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, August 2000, vol. 1, pp. 262~265.

60.       Hsie-Chia Chang, and C. Bernard Shung, “A (208,192) Reed-Solomon decoder for DVD application,” in IEEE Int. Conf. on Communications (ICC), Atlanta, GA, June 1998, pp.957~960.

61.       Hsie-Chia Chang, and C. Bernard Shung, “A RS-PC decoder for DVD applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, February 1998, pp. 390~391.

(C)     專利

1.     鄭延修、翁政吉、唐正浩、林建青、張錫嘉、李鎮宜、蘇育德,利用通道演算法用於排序及解排序之蝴蝶型網路,” 中華民國專利申請第98125946號,96427日。(公告號:200950351(經濟部科專計畫)

2.     廖彥欽、張錫嘉,用於通道解碼系統之候選人清單擴增裝置及其方法,”中華民國與美國專利申請第98100296號,9816日。(公告號:201006164(國科會NSC 96-2220-E-009-030

3.     吳昭逸、廖彥欽、張錫嘉,適用於縮短式BCH碼或Reed-Solomon碼之解碼方式與裝置,” 中華民國專利發明第I357725號,10121日。(經濟部94-EC-17-A-01-S1-048

4.     陸志豪、廖彥欽、李鎮宜、張錫嘉、許雅三,應用於低密度對稱檢查碼(LDPC)解碼器之運算方法及其電路,” 中華民國專利發明第I34646210081日。(經濟部科專93-EC-17-A-03-S1-0005

5.     翁政吉、李永裕、賴名威、林建青、張錫嘉、李鎮宜,應用於迭代解碼之多層級網路架構及其傳輸方法,” 中華民國專利發明第I343190號,10061日。(經濟部科專 95-EC-17-A-01-S1-048

6.     陸志豪、林建青、李鎮宜、張錫嘉、許雅三,多模多平行度資料交換方法及其裝置,”中華民國專利發明第I339955號,10041日。(經濟部科專93-EC-17-A-03- S1-0005)。

7.     陸志豪、林建青、李鎮宜、許雅三、張錫嘉,用於通訊系統的資料交換裝置及方法,” 中華民國專利發明第I339944號,10041日。(國科會NSC94-2220-E-009-027

8.     廖彥欽、張錫嘉,乘法器進位位元之估計方法與裝置,” 中華民國專利發明第I338854號,100311日。(經濟部科專94-EC-17-A-01-S1-048

9.     廖彥欽、林建青、張錫嘉、劉志尉,應用於信度傳播演算法的自動補償方法與裝置,” 中華民國專利發明I318507號,981211日。(國科會NSC 93-2220-E-009-027

10. 李鎮宜、林建青、林凱立、張錫嘉, “用於更新低密度配類核對(LDPC)碼解碼器之核對節點的方法裝置,” 中華民國專利發明I291290號,961211。(國科會NSC 93-2220-E-009-033

11. 黃維宏、張錫嘉、王晉傑,迴旋式打散/反打散技術之系統與方法,” 中華民國專利發明I264653號,951021

12. 林建青、張錫嘉、李鎮宜, ”結合格狀調變碼(TCM)與低複雜度對稱檢查碼之方法,” 中華民國專利發明I255608號,95521。(國科會NSC 93-2220-E-009-033

13. 吳介琮、汪大暉、張錫嘉, “組合多準位記憶單元並使其具備錯誤更正機制的方法,” 中華民國專利發明I243376號,941111。(國科會)

14. 張錫嘉、朱清和, “讀取記憶體之方法,” 中華民國專利發明第240167號,94921日。

15. 胡逸光、楊金彬、張錫嘉, “交錯式週期碼之編碼方法與裝置,” 中華民國專利發明第226758號,94111日。

16. 李鎮宜、張錫嘉、林建青, “在解碼錯誤訂正碼時用以計算徵兆多項式之方法,” 中華民國專利發明第174118, 931220日。(國科會NSC 90-2218-E-009-035

17. 李鎮宜、張錫嘉, “解碼錯誤訂正碼時用以解答鍵方程式多項式之方法及其裝置,” 中華民國專利發明第193271, 93419(國科會NSC 89-2215-E-009-053

18. 張錫嘉、項春申, “在解碼錯誤訂正碼時用以解答鍵方程式多項式之方法及其裝置,” 中華民國專利發明第112897, 89311

19. 陸志豪、廖彥欽、李鎮宜、許雅三、張錫嘉,應用於低密度對稱檢查碼(LDPC)解碼器之運算方法及其電路/低密度パリティ検査(LDPC)デコーダに応用する演算方法、及び、その回路を提供する,” 日本專利特許第4852061號,101111日。(經濟部科專93-EC-17-A-03-S1-0005

20. Yen-Chin Liao and Hsie-Chia Chang, “Method and apparatus for carry estimation of reduced-width multipliers,” has been filed as U.S. Patent pending, 787716, April 17, 2007. pub. no. 20080159441(經濟部科專94-EC-17-A-01-S1-048

21. Yen-Chin Liao and Hsie-Chia Chang, “Method and apparatus of candidate list augmentation for channel coding system,” U.S. Patent 8255775, August 28, 2012.(自費申請)

22. Chih-Hao Liu, Yen-Chin Liao, Chen-Yi Lee, Hsie-Chia Chang, and Yar-Sun Hsu, “Operating Method Applied to Low Density Parity Check (LDPC) Decoder and Circuit Thereof”, U.S. Patent 8108762, January 31, 2012.(經濟部科專93-EC-17-A-03-S1-0005

23. Yi-Kwang Hu; Jin-Bin Yang, and Hsi-Chia Chang, “Encoding method and apparatus for cross interleaved cyclic codes,” U.S. Patent 7954040, May 31, 2011.

24. Jau-Yet Wu, Yen-Chin Liao and Hsie-Chia Chang, ”Method and apparatus for decoding shorten BCH or Reed-Solomon codes,” U.S. Patent 7941734, May 10, 2011.(經濟部科專經濟部 94-EC-17-A-01-S1-048

25. Chen-Yi Lee, Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, and Yar-Sun Hsu, “Method and Apparatus for Switching Data in Communication System,” U.S. Patent 7724772, May 25, 2010.(國科會NSC94-2220-E-009-027

26. Chen-Yi Lee, Chih-Hau Liu, Chien-Ching Lin, Hsie-Chia Chang , and Yar-Sun Hsu, “Method and Apparatus for Switching Data in Communication System,U.S. Patent 7724770, May 25, 2010.(國科會NSC94-2220-E-009-027

27. Cheng-Chi Wong, Yung-Yu Lee, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, and Chen-Yi Lee, ”Apparatus of multi-stage network for iterative decoding and method thereof,” U.S. Patent 7724163, May 25, 2010.(經濟部科專 95-EC-17-A-01-S1-048

28. Chih-Hao Liu, Chien-Ching Lin, Chen-Yi Lee, Hsie-Chia Chang, and Yar-Sun Hsu, “Multi-mode multi-parallelism data exchange method and device thereof,” U.S. Patent 7719442, May 18, 2010.(經濟部科專93-EC-17-A-03-S1-0005

29. Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, and Chih-Wei Liu, “Method and apparatus using self-compensation technique for brief propagation algorithms,” U.S. Patent 7631250, December 8, 2009(國科會NSC 93-2220-E-009-027

30. Hsi-Chia Chang and Chin-Huo Chu, “Method and apparatus for accessing memory,” U.S. Patent 7607067, October 20, 2009.

31. Yi-Kwang Hu; Jin-Bin Yang, and Hsi-Chia Chang, “Encoding method and apparatus for cross interleaved cyclic codes,” U.S. Patent 7472333, December 30, 2008.

32. Wei-Hung Huang, Hsi-Chia Chang, Ching-Chieh Wang, “Method and apparatus for convolutional interleaving/de-interleaving technique,” U.S. Patent 7363552, April 22, 2008.

33. Jieh-Tsorng Wu, Ta-Hui Wang, and Hsie-Chia Chang, “Method of combining multilevel memory cells for an error correction scheme,” U.S. Patent 7243277, July 10, 2007.(國科會)

34. Chen-Yi Lee, Hsie-Chia Chang, and Chien-Ching Lin, “Method for calculating syndrome polynomial in decoding error correction codes,” U.S. Patent 6954892, October 11, 2005.(國科會NSC90-2218-E-009-035

35. Hsie-Chia Chang and C. Bernard Shung, “Method and apparatus for solving key equation polynomials in decoding error correction codes,” U.S. Patent 6119262, September 12, 2000.

 

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