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2012

 
 
Applications:                                                                             製程之多碼率渦輪解碼器                   
Designer: 林振揚

Descriptions

此晶片是以台積電40nm製程之多碼率渦輪解碼器。首次利用渦輪碼的reciprocal dual trellis來設計多碼率之功能,並且使用兩套soft in/soft out解碼器來提升吞吐量。本晶片可提供1/31/22/34/58/9之碼率,在供應電壓為0.9伏特下,可提供535Mbps之吞吐量。

晶片面積: 2220.04um x 1520.04um

操作頻率: 250MHz

功率消耗:281mW

 
Chip Title: 高吞吐量低延遲關鍵方程式求解器

Features1.     高吞吐量 2. 低延遲3. 低面積

Applications1.     BCH 解碼器 2. 固態硬碟

Designer:蔡泓原

Descriptions

針對 BCH的關鍵方程求解器硬體,提出了一種低延遲和低面積的架透過重新安排初始值、硬體共用以及將計算過程中的閒置部分去除的技巧,將傳統的硬體架構複雜度大幅降低。對於(1824416384;124BCH碼,提出關鍵方程求解器與傳統架構比較,可以省下42%左右的邏輯閘數量。在量測上,則是可以運作在 198兆赫的頻率下,使吞吐量達到12.6吉位元率。此吞吐量已可支援市面上現行ThunderboltPCIe的傳輸介面規

 
 An Fully Parallel BCH Codec with Double Error Correcting Capability for NOR Flash Memory Systems

Latency-constrained memories are utilized for the high throughput systems. As the memory process is scaling down, error control codes are used to improve reliability. Thus, a double error correcting (DEC) BCH codec is designed for latency-constrained memory systems such as NOR flash memories. To meet the design target of latency-constrained memory systems, the fully parallel architecture with huge hardware cost is utilized to process both the encoding and decoding scheme within one clock cycle. Since the BCH encoder and decoder will not be activated simultaneously in NOR flash applications, we combine the encoder and syndrome calculator based on the property of minimal polynomials in order to efficiently arrange silicon area. Furthermore, we developed two new expressions of error location polynomials based on matrix operations to reduce the number of constant finite filed multipliers (CFFMs) in Chien search, which dominates the hardware complexity of decoder. According to 90 nm CMOS technology, our proposed DEC BCH codec chip with 256-bit data length can achieve 264 MHz with 28.2K gate count. Note that this chip contains test mode on account of the limited pad number.


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