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x64 Opcode and Instruction Reference Home

one-byte opcodes index:

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

two-byte opcodes (0F..) index:

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
pf0Fposooprocstmrlxmnemonicop1op2op3op4iexttested fmodif fdef fundef ff valuesdescription, notes                                        
00rLADDr/m8r8o..szapco..szapcAdd
01rLADDr/m16/32/64r16/32/64o..szapco..szapcAdd
02rADDr8r/m8o..szapco..szapcAdd
03rADDr16/32/64r/m16/32/64o..szapco..szapcAdd
04ADDALimm8o..szapco..szapcAdd
05ADDrAXimm16/32o..szapco..szapcAdd
06EinvalidInvalid Instruction in 64-Bit Mode
07EinvalidInvalid Instruction in 64-Bit Mode
08rLORr/m8r8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
09rLORr/m16/32/64r16/32/64o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0ArORr8r/m8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0BrORr16/32/64r/m16/32/64o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0CORALimm8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0DORrAXimm16/32o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0EEinvalidInvalid Instruction in 64-Bit Mode
0FTwo-byte Instructions
10rLADCr/m8r8.......co..szapco..szapcAdd with Carry
11rLADCr/m16/32/64r16/32/64.......co..szapco..szapcAdd with Carry
12rADCr8r/m8.......co..szapco..szapcAdd with Carry
13rADCr16/32/64r/m16/32/64.......co..szapco..szapcAdd with Carry
14ADCALimm8.......co..szapco..szapcAdd with Carry
15ADCrAXimm16/32.......co..szapco..szapcAdd with Carry
16EinvalidInvalid Instruction in 64-Bit Mode
17EinvalidInvalid Instruction in 64-Bit Mode
18rLSBBr/m8r8.......co..szapco..szapcInteger Subtraction with Borrow
19rLSBBr/m16/32/64r16/32/64.......co..szapco..szapcInteger Subtraction with Borrow
1ArSBBr8r/m8.......co..szapco..szapcInteger Subtraction with Borrow
1BrSBBr16/32/64r/m16/32/64.......co..szapco..szapcInteger Subtraction with Borrow
1CSBBALimm8.......co..szapco..szapcInteger Subtraction with Borrow
1DSBBrAXimm16/32.......co..szapco..szapcInteger Subtraction with Borrow
1EEinvalidInvalid Instruction in 64-Bit Mode
1FEinvalidInvalid Instruction in 64-Bit Mode
20rLANDr/m8r8o..szapco..sz.pc.....a..o......cLogical AND
21rLANDr/m16/32/64r16/32/64o..szapco..sz.pc.....a..o......cLogical AND
22rANDr8r/m8o..szapco..sz.pc.....a..o......cLogical AND
23rANDr16/32/64r/m16/32/64o..szapco..sz.pc.....a..o......cLogical AND
24ANDALimm8o..szapco..sz.pc.....a..o......cLogical AND
25ANDrAXimm16/32o..szapco..sz.pc.....a..o......cLogical AND
26EnullNull Prefix in 64-bit Mode
27EinvalidInvalid Instruction in 64-Bit Mode
28rLSUBr/m8r8o..szapco..szapcSubtract
29rLSUBr/m16/32/64r16/32/64o..szapco..szapcSubtract
2ArSUBr8r/m8o..szapco..szapcSubtract
2BrSUBr16/32/64r/m16/32/64o..szapco..szapcSubtract
2CSUBALimm8o..szapco..szapcSubtract
2DSUBrAXimm16/32o..szapco..szapcSubtract
2EEnullNull Prefix in 64-bit Mode
2FEinvalidInvalid Instruction in 64-Bit Mode
30rLXORr/m8r8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
31rLXORr/m16/32/64r16/32/64o..szapco..sz.pc.....a..o......cLogical Exclusive OR
32rXORr8r/m8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
33rXORr16/32/64r/m16/32/64o..szapco..sz.pc.....a..o......cLogical Exclusive OR
34XORALimm8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
35XORrAXimm16/32o..szapco..sz.pc.....a..o......cLogical Exclusive OR
36EnullNull Prefix in 64-bit Mode
37EinvalidInvalid Instruction in 64-Bit Mode
38rCMPr/m8r8o..szapco..szapcCompare Two Operands
39rCMPr/m16/32/64r16/32/64o..szapco..szapcCompare Two Operands
3ArCMPr8r/m8o..szapco..szapcCompare Two Operands
3BrCMPr16/32/64r/m16/32/64o..szapco..szapcCompare Two Operands
3CCMPALimm8o..szapco..szapcCompare Two Operands
3DCMPrAXimm16/32o..szapco..szapcCompare Two Operands
3EEnullNull Prefix in 64-bit Mode
3FEinvalidInvalid Instruction in 64-Bit Mode
40EREXAccess to new 8-bit registers
41EREX.BExtension of r/m field, base field, or opcode reg field
42EREX.XExtension of SIB index field
43EREX.XBREX.X and REX.B combination
44EREX.RExtension of ModR/M reg field
45EREX.RBREX.R and REX.B combination
46EREX.RXREX.R and REX.X combination
47EREX.RXBREX.R, REX.X and REX.B combination
48EREX.W64 Bit Operand Size
49EREX.WBREX.W and REX.B combination
4AEREX.WXREX.W and REX.X combination
4BEREX.WXBREX.W, REX.X and REX.B combination
4CEREX.WRREX.W and REX.R combination
4DEREX.WRBREX.W, REX.R and REX.B combination
4EEREX.WRXREX.W, REX.R and REX.X combination
4FEREX.WRXBREX.W, REX.R, REX.X and REX.B combination
50+rEPUSHr64/16Push Word, Doubleword or Quadword Onto the Stack
58+rEPOPr64/16Pop a Value from the Stack
60EinvalidInvalid Instruction in 64-Bit Mode
61EinvalidInvalid Instruction in 64-Bit Mode
62EinvalidInvalid Instruction in 64-Bit Mode
63rEMOVSXDr32/64r/m32Move with Sign-Extension
64FSFSFS segment override prefix
65GSGSGS segment override prefix
66no mnemonicOperand-size override prefix
66Mno mnemonicsse2Precision-size override prefix
67no mnemonicAddress-size override prefix
68PUSHimm16/32Push Word, Doubleword or Quadword Onto the Stack
69rIMULr16/32/64r/m16/32/64imm16/32o..szapco......c...szap.Signed Multiply
6APUSHimm8Push Word, Doubleword or Quadword Onto the Stack
6BrIMULr16/32/64r/m16/32/64imm8o..szapco......c...szap.Signed Multiply
6Cf1INSm8DX.d......Input from Port to String
INSBm8DX
6Df1INSm16DX.d......Input from Port to String
INSWm16DX
6Df1INSm16/32DX.d......Input from Port to String
INSDm32DX
6Ef1OUTSDXm8.d......Output String to Port
OUTSBDXm8
6Ff1OUTSDXm16.d......Output String to Port
OUTSWDXm16
6Ff1OUTSDXm16/32.d......Output String to Port
OUTSDDXm32
70JOrel8o.......Jump short if overflow (OF=1)
71JNOrel8o.......Jump short if not overflow (OF=0)
72JBrel8.......cJump short if below/not above or equal/carry (CF=1)
JNAErel8
JCrel8
73JNBrel8.......cJump short if not below/above or equal/not carry (CF=0)
JAErel8
JNCrel8
74JZrel8....z...Jump short if zero/equal (ZF=0)
JErel8
75JNZrel8....z...Jump short if not zero/not equal (ZF=1)
JNErel8
76JBErel8....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNArel8
77JNBErel8....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JArel8
78JSrel8...s....Jump short if sign (SF=1)
79JNSrel8...s....Jump short if not sign (SF=0)
7AJPrel8......p.Jump short if parity/parity even (PF=1)
JPErel8
7BJNPrel8......p.Jump short if not parity/parity odd
JPOrel8
7CJLrel8o..s....Jump short if less/not greater (SF!=OF)
JNGErel8
7DJNLrel8o..s....Jump short if not less/greater or equal (SF=OF)
JGErel8
7EJLErel8o..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNGrel8
7FJNLErel8o..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JGrel8
800LADDr/m8imm8o..szapco..szapcAdd
801LORr/m8imm8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
802LADCr/m8imm8.......co..szapco..szapcAdd with Carry
803LSBBr/m8imm8.......co..szapco..szapcInteger Subtraction with Borrow
804LANDr/m8imm8o..szapco..sz.pc.....a..o......cLogical AND
805LSUBr/m8imm8o..szapco..szapcSubtract
806LXORr/m8imm8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
807CMPr/m8imm8o..szapco..szapcCompare Two Operands
810LADDr/m16/32/64imm16/32o..szapco..szapcAdd
811LORr/m16/32/64imm16/32o..szapco..sz.pc.....a..o......cLogical Inclusive OR
812LADCr/m16/32/64imm16/32.......co..szapco..szapcAdd with Carry
813LSBBr/m16/32/64imm16/32.......co..szapco..szapcInteger Subtraction with Borrow
814LANDr/m16/32/64imm16/32o..szapco..sz.pc.....a..o......cLogical AND
815LSUBr/m16/32/64imm16/32o..szapco..szapcSubtract
816LXORr/m16/32/64imm16/32o..szapco..sz.pc.....a..o......cLogical Exclusive OR
817CMPr/m16/32/64imm16/32o..szapco..szapcCompare Two Operands
82EinvalidInvalid Instruction in 64-Bit Mode
830LADDr/m16/32/64imm8o..szapco..szapcAdd
831LORr/m16/32/64imm8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
832LADCr/m16/32/64imm8.......co..szapco..szapcAdd with Carry
833LSBBr/m16/32/64imm8.......co..szapco..szapcInteger Subtraction with Borrow
834LANDr/m16/32/64imm8o..szapco..sz.pc.....a..o......cLogical AND
835LSUBr/m16/32/64imm8o..szapco..szapcSubtract
836LXORr/m16/32/64imm8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
837CMPr/m16/32/64imm8o..szapco..szapcCompare Two Operands
84rTESTr/m8r8o..szapco..sz.pc.....a..o......cLogical Compare
85rTESTr/m16/32/64r16/32/64o..szapco..sz.pc.....a..o......cLogical Compare
86rLXCHGr8r/m8Exchange Register/Memory with Register
87rLXCHGr16/32/64r/m16/32/64Exchange Register/Memory with Register
88rMOVr/m8r8Move
89rMOVr/m16/32/64r16/32/64Move
8ArMOVr8r/m8Move
8BrMOVr16/32/64r/m16/32/64Move
8CrMOVm16SregMove
MOVr16/32/64Sreg
8DrLEAr16/32/64mLoad Effective Address
8ErMOVSregr/m16Move
8F0POPr/m16/32Pop a Value from the Stack
8F0EPOPr/m64/16Pop a Value from the Stack
90+rXCHGr16/32/64rAXExchange Register/Memory with Register
90D1NOPNo Operation
F390PAUSEsse2Spin Loop Hint
98ECBWAXALConvert
CWDEEAXAX
CDQERAXEAX
99ECWDDXAXConvert
CDQEDXEAX
CQORDXRAX
9AEinvalidInvalid Instruction in 64-Bit Mode
9BFWAIT01230123Check pending unmasked floating-point exceptions
WAIT
9Bno mnemonic01230123Wait Prefix
9CEPUSHFFlagsPush rFLAGS Register onto the Stack
PUSHFQRFlags
9DEPOPFFlagsPop Stack into rFLAGS Register
POPFQRFlags
9ED2SAHFAH...szapc...szapcStore AH into Flags
9FD2LAHFAH...szapcLoad Status Flags into AH Register
A0MOVALmoffs8Move
A1MOVrAXmoffs16/32/64Move
A2MOVmoffs8ALMove
A3MOVmoffs16/32/64rAXMove
A4MOVSm8m8.d......Move Data from String to String
MOVSBm8m8
A5EMOVSm16/32/64m16/32/64.d......Move Data from String to String
MOVSWm16m16
MOVSDm32m32
MOVSQm64m64
A6CMPSm8m8.d......o..szapco..szapcCompare String Operands
CMPSBm8m8
A7ECMPSm16/32/64m16/32/64.d......o..szapco..szapcCompare String Operands
CMPSWm16m16
CMPSDm32m32
CMPSQm64m64
A8TESTALimm8o..szapco..sz.pc.....a..o......cLogical Compare
A9TESTrAXimm16/32o..szapco..sz.pc.....a..o......cLogical Compare
AASTOSm8AL.d......Store String
STOSBm8AL
ABESTOSm16/32/64rAX.d......Store String
STOSWm16AX
STOSDm32EAX
STOSQm64RAX
ACLODSALm8.d......Load String
LODSBALm8
ADELODSrAXm16/32/64.d......Load String
LODSWAXm16
LODSDEAXm32
LODSQRAXm64
AESCASm8AL.d......o..szapco..szapcScan String
SCASBm8AL
AFESCASm16/32/64rAX.d......o..szapco..szapcScan String
SCASWm16AX
SCASDm32EAX
SCASQm64RAX
B0+rMOVr8imm8Move
B8+rMOVr16/32/64imm16/32/64Move
C00ROLr/m8imm8o..szapco..szapco.......Rotate
C01RORr/m8imm8o..szapco..szapco.......Rotate
C02RCLr/m8imm8.......co..szapco..szapco.......Rotate
C03RCRr/m8imm8.......co..szapco..szapco.......Rotate
C04SHLr/m8imm8o..szapco..sz.pco....a.cShift
SALr/m8imm8
C05SHRr/m8imm8o..szapco..sz.pco....a.cShift
C06U3SALr/m8imm8o..szapco..sz.pco....a.cShift
SHLr/m8imm8
C07SARr/m8imm8o..szapco..sz.pco....a..Shift
C10ROLr/m16/32/64imm8o..szapco..szapco.......Rotate
C11RORr/m16/32/64imm8o..szapco..szapco.......Rotate
C12RCLr/m16/32/64imm8.......co..szapco..szapco.......Rotate
C13RCRr/m16/32/64imm8.......co..szapco..szapco.......Rotate
C14SHLr/m16/32/64imm8o..szapco..sz.pco....a.cShift
SALr/m16/32/64imm8
C15SHRr/m16/32/64imm8o..szapco..sz.pco....a.cShift
C16U3SALr/m16/32/64imm8o..szapco..sz.pco....a.cShift
SHLr/m16/32/64imm8
C17SARr/m16/32/64imm8o..szapco..sz.pco....a..Shift
C2RETNimm16Return from procedure
C3RETNReturn from procedure
C4EinvalidInvalid Instruction in 64-Bit Mode
C5EinvalidInvalid Instruction in 64-Bit Mode
C60MOVr/m8imm8Move
C70MOVr/m16/32/64imm16/32Move
C8EENTERrBPimm16imm8Make Stack Frame for Procedure Parameters
C9ELEAVErBPHigh Level Procedure Exit
CAfRETFimm16Return from procedure
CBfRETFReturn from procedure
CCfINT3eFlags..i.......i.......i.....Call to Interrupt Procedure
CDfINTimm8eFlags..i.......i.......i.....Call to Interrupt Procedure
CEfINTOeFlagso.........i.......i.......i.....Call to Interrupt Procedure
CFEfIRETFlagsInterrupt Return
IRETDEFlags
IRETQRFlags
D00ROLr/m81o..szapco..szapcRotate
D01RORr/m81o..szapco..szapcRotate
D02RCLr/m81.......co..szapco..szapcRotate
D03RCRr/m81.......co..szapco..szapcRotate
D04SHLr/m81o..szapco..sz.pc.....a..Shift
SALr/m81
D05SHRr/m81o..szapco..sz.pc.....a..Shift
D06U3SALr/m81o..szapco..sz.pc.....a..Shift
SHLr/m81
D07SARr/m81o..szapco..sz.pc.....a..Shift
D10ROLr/m16/32/641o..szapco..szapcRotate
D11RORr/m16/32/641o..szapco..szapcRotate
D12RCLr/m16/32/641.......co..szapco..szapcRotate
D13RCRr/m16/32/641.......co..szapco..szapcRotate
D14SHLr/m16/32/641o..szapco..sz.pc.....a..Shift
SALr/m16/32/641
D15SHRr/m16/32/641o..szapco..sz.pc.....a..Shift
D16U3SALr/m16/32/641o..szapco..sz.pc.....a..Shift
SHLr/m16/32/641
D17SARr/m16/32/641o..szapco..sz.pc.....a..Shift
D20ROLr/m8CLo..szapco..szapco.......Rotate
D21RORr/m8CLo..szapco..szapco.......Rotate
D22RCLr/m8CL.......co..szapco..szapco.......Rotate
D23RCRr/m8CL.......co..szapco..szapco.......Rotate
D24SHLr/m8CLo..szapco..sz.pco....a.cShift
SALr/m8CL
D25SHRr/m8CLo..szapco..sz.pco....a.cShift
D26U3SALr/m8CLo..szapco..sz.pco....a.cShift
SHLr/m8CL
D27SARr/m8CLo..szapco..sz.pco....a..Shift
D30ROLr/m16/32/64CLo..szapco..szapco.......Rotate
D31RORr/m16/32/64CLo..szapco..szapco.......Rotate
D32RCLr/m16/32/64CL.......co..szapco..szapco.......Rotate
D33RCRr/m16/32/64CL.......co..szapco..szapco.......Rotate
D34SHLr/m16/32/64CLo..szapco..sz.pco....a.cShift
SALr/m16/32/64CL
D35SHRr/m16/32/64CLo..szapco..sz.pco....a.cShift
D36U3SALr/m16/32/64CLo..szapco..sz.pco....a.cShift
SHLr/m16/32/64CL
D37SARr/m16/32/64CLo..szapco..sz.pc.....a..Shift
D4EinvalidInvalid Instruction in 64-Bit Mode
D5EinvalidInvalid Instruction in 64-Bit Mode
D6EinvalidInvalid Instruction in 64-Bit Mode
D7XLATALm8Table Look-up Translation
XLATBALm8
D80FADDSTm32real0123.1..0.23Add
FADDSTSTi
D81FMULSTm32real0123.1..0.23Multiply
FMULSTSTi
D82FCOMSTSTi/m32real01230123Compare Real
D8D12FCOMSTST101230123Compare Real
D83pFCOMPSTSTi/m32real01230123Compare Real and Pop
D8D93pFCOMPSTST101230123Compare Real and Pop
D84FSUBSTm32real0123.1..0.23Subtract
FSUBSTSTi
D85FSUBRSTm32real0123.1..0.23Reverse Subtract
FSUBRSTSTi
D86FDIVSTm32real0123.1..0.23Divide
FDIVSTSTi
D87FDIVRSTm32real0123.1..0.23Reverse Divide
FDIVRSTSTi
D90sFLDSTSTi/m32real0123.1..0.23Load Floating Point Value
D91FXCHSTSTi0123.1..0.23Exchange Register Contents
D9C91FXCHSTST10123.1..0.23Exchange Register Contents
D92FSTm32realST0123.1..0.23Store Floating Point Value
D9D02FNOP01230123No Operation
D93pFSTPm32realST0123.1..0.23Store Floating Point Value and Pop
D93U9pFSTP1STiST0123.1..0.23Store Floating Point Value and Pop
D94FLDENVm14/2801230123Load x87 FPU Environment
D9E04FCHSST0123.1..0.23Change Sign
D9E14FABSST0123.1..0.23Absolute Value
D9E44FTSTST01230123Test
D9E54FXAMST01230123Examine
D95FLDCWm1601230123Load x87 FPU Control Word
D9E85sFLD1ST0123.1..0.23Load Constant +1.0
D9E95sFLDL2TST0123.1..0.23Load Constant log210
D9EA5sFLDL2EST0123.1..0.23Load Constant log2e
D9EB5sFLDPIST0123.1..0.23Load Constant π
D9EC5sFLDLG2ST0123.1..0.23Load Constant log102
D9ED5sFLDLN2ST0123.1..0.23Load Constant loge2
D9EE5sFLDZST0123.1..0.23Load Constant +0.0
D96FNSTENVm14/2801230123Store x87 FPU Environment
9BD96FSTENVm14/2801230123Store x87 FPU Environment
D9F06F2XM1ST0123.1..0.23Compute 2x-1
D9F16pFYL2XST1ST0123.1..0.23Compute y × log2x and Pop
D9F26sFPTANST0123.12.0..3Partial Tangent
D9F36pFPATANST1ST0123.1..0.23Partial Arctangent and Pop
D9F46sFXTRACTST0123.1..0.23Extract Exponent and Significand
D9F56FPREM1STST101230123IEEE Partial Remainder
D9F66FDECSTP0123.1..0.23.0..Decrement Stack-Top Pointer
D9F76FINCSTP0123.1..0.23.0..Increment Stack-Top Pointer
D97FNSTCWm1601230123Store x87 FPU Control Word
9BD97FSTCWm1601230123Store x87 FPU Control Word
D9F87FPREMSTST101230123Partial Remainder (for compatibility with i8087 and i287)
D9F97pFYL2XP1ST1ST0123.1..0.23Compute y × log2(x+1) and Pop
D9FA7FSQRTST0123.1..0.23Square Root
D9FB7sFSINCOSST0123.12.0..3Sine and Cosine
D9FC7FRNDINTST0123.1..0.23Round to Integer
D9FD7FSCALESTST10123.1..0.23Scale
D9FE7FSINST0123.12.0..3Sine
D9FF7FCOSST0123.12.0..3Cosine
DA0FIADDSTm32int0123.1..0.23Add
DA0FCMOVBSTSTi.......c0123.1..0.23FP Conditional Move - below (CF=1)
DA1FIMULSTm32int0123.1..0.23Multiply
DA1FCMOVESTSTi....z...0123.1..0.23FP Conditional Move - equal (ZF=1)
DA2FICOMSTm32int01230123Compare Integer
DA2FCMOVBESTSTi....z...0123.1..0.23FP Conditional Move - below or equal (CF=1 or ZF=1)
DA3pFICOMPSTm32int01230123Compare Integer and Pop
DA3FCMOVUSTSTi......p.0123.1..0.23FP Conditional Move - unordered (PF=1)
DA4FISUBSTm32int0123.1..0.23Subtract
DA5FISUBRSTm32int0123.1..0.23Reverse Subtract
DAE95PFUCOMPPSTST101230123Unordered Compare Floating Point Values and Pop Twice
DA6FIDIVSTm32int0123.1..0.23Divide
DA7FIDIVRSTm32int0123.1..0.23Reverse Divide
DB0sFILDSTm32int0123.1..0.23Load Integer
DB0FCMOVNBSTSTi.......c0123.1..0.23FP Conditional Move - not below (CF=0)
DB1pFISTTPm32intSTsse30123.1..0.23.0..Store Integer with Truncation and Pop
DB1FCMOVNESTSTi....z...0123.1..0.23FP Conditional Move - not equal (ZF=0)
DB2FISTm32intST0123.1..0.23Store Integer
DB2FCMOVNBESTSTi....z...0123.1..0.23FP Conditional Move - below or equal (CF=0 and ZF=0)
DB3pFISTPm32intST0123.1..0.23Store Integer and Pop
DB3FCMOVNUSTSTi......p.0123.1..0.23FP Conditional Move - not unordered (PF=0)
DBE04D6FNENInopTreated as Integer NOP
DBE14D6FNDISInopTreated as Integer NOP
DBE24FNCLEX01230123Clear Exceptions
9BDBE24FCLEX01230123Clear Exceptions
DBE34FNINIT01230000Initialize Floating-Point Unit
9BDBE34FINIT01230000Initialize Floating-Point Unit
DBE44D7FNSETPMnopTreated as Integer NOP
DB5sFLDSTm80real0123.1..0.23Load Floating Point Value
DB5FUCOMISTSTio...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS
DB6FCOMISTSTio...z.pc .1..o...z.pc .1..o.......Compare Floating Point Values and Set EFLAGS
DB7pFSTPm80realST0123.1..0.23Store Floating Point Value and Pop
DC0FADDSTm64real0123.1..0.23Add
DC0FADDSTiST0123.1..0.23Add
DC1FMULSTm64real0123.1..0.23Multiply
DC1FMULSTiST0123.1..0.23Multiply
DC2FCOMSTm64real01230123Compare Real
DC2U9FCOM2STSTi01230123Compare Real
DC3pFCOMPSTm64real01230123Compare Real and Pop
DC3U9pFCOMP3STSTi01230123Compare Real and Pop
DC4FSUBSTm64real0123.1..0.23Subtract
DC4FSUBRSTiST0123.1..0.23Reverse Subtract
DC5FSUBRSTm64real0123.1..0.23Reverse Subtract
DC5FSUBSTiST0123.1..0.23Subtract
DC6FDIVSTm64real0123.1..0.23Divide
DC6FDIVRSTiST0123.1..0.23Reverse Divide
DC7FDIVRSTm64real0123.1..0.23Reverse Divide
DC7FDIVSTiST0123.1..0.23Divide and Pop
DD0sFLDSTm64real0123.1..0.23Load Floating Point Value
DD0FFREESTi01230123Free Floating-Point Register
DD1pFISTTPm64intSTsse30123.1..0.23.0..Store Integer with Truncation and Pop
DD1U9FXCH4STSTi0123.1..0.23Exchange Register Contents
DD2FSTm64realST0123.1..0.23Store Floating Point Value
DD2FSTSTSTi0123.1..0.23Store Floating Point Value
DD3pFSTPm64realST0123.1..0.23Store Floating Point Value and Pop
DD3pFSTPSTSTi0123.1..0.23Store Floating Point Value and Pop
DD4FRSTORSTST1ST2...01230123Restore x87 FPU State
DD4FUCOMSTSTi01230123Unordered Compare Floating Point Values
DDE14FUCOMSTST101230123Unordered Compare Floating Point Values
DD5pFUCOMPSTSTi01230123Unordered Compare Floating Point Values and Pop
DDE95pFUCOMPSTST101230123Unordered Compare Floating Point Values and Pop
DD6FNSAVEm94/108STST1...012301230000Store x87 FPU State
9BDD6FSAVEm94/108STST1...012301230000Store x87 FPU State
DD7FNSTSWm1601230123Store x87 FPU Status Word
9BDD7FSTSWm1601230123Store x87 FPU Status Word
DE0FIADDSTm16int0123.1..0.23Add
DE0pFADDPSTiST0123.1..0.23Add and Pop
DEC10pFADDPST1ST0123.1..0.23Add and Pop
DE1FIMULSTm16int0123.1..0.23Multiply
DE1pFMULPSTiST0123.1..0.23Multiply and Pop
DEC91pFMULPST1ST0123.1..0.23Multiply and Pop
DE2FICOMSTm16int01230123Compare Integer
DE2U9pFCOMP5STSTi01230123Compare Real and Pop
DE3pFICOMPSTm16int01230123Compare Integer and Pop
DED93PFCOMPPSTST101230123Compare Real and Pop Twice
DE4FISUBSTm16int0123.1..0.23Subtract
DE4pFSUBRPSTiST0123.1..0.23Reverse Subtract and Pop
DEE14pFSUBRPST1ST0123.1..0.23Reverse Subtract and Pop
DE5FISUBRSTm16int0123.1..0.23Reverse Subtract
DE5pFSUBPSTiST0123.1..0.23Subtract and Pop
DEE95pFSUBPST1ST0123.1..0.23Subtract and Pop
DE6FIDIVSTm16int0123.1..0.23Divide
DE6pFDIVRPSTiST0123.1..0.23Reverse Divide and Pop
DEF16pFDIVRPST1ST0123.1..0.23Reverse Divide and Pop
DE7FIDIVRSTm16int0123.1..0.23Reverse Divide
DE7pFDIVPSTiST0123.1..0.23Divide and Pop
DEF97pFDIVPST1ST0123.1..0.23Divide and Pop
DF0sFILDSTm16int0123.1..0.23Load Integer
DF0D8pFFREEPSTi01230123Free Floating-Point Register and Pop
DF1pFISTTPm16intSTsse30123.1..0.23.0..Store Integer with Truncation and Pop
DF1U9FXCH7STSTi0123.1..0.23Exchange Register Contents
DF2FISTm16intST0123.1..0.23Store Integer
DF2U9pFSTP8STiST0123.1..0.23Store Floating Point Value and Pop
DF3pFISTPm16intST0123.1..0.23Store Integer and Pop
DF3U9pFSTP9STiST0123.1..0.23Store Floating Point Value and Pop
DF4sFBLDSTm80dec0123.1..0.23Load Binary Coded Decimal
DFE04FNSTSWAX01230123Store x87 FPU Status Word
9BDFE04FSTSWAX01230123Store x87 FPU Status Word
DF5sFILDSTm64int0123.1..0.23Load Integer
DF5pFUCOMIPSTSTio...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS and Pop
DF6pFBSTPm80decST0123.1..0.23Store BCD Integer and Pop
DF6pFCOMIPSTSTio...z.pc .1..o...z.pc .1..o.......Compare Floating Point Values and Set EFLAGS and Pop
DF7pFISTPm64intST0123.1..0.23Store Integer and Pop
E0D32ELOOPNZrCXrel8....z...Decrement count; Jump short if count!=0 and ZF=0
LOOPNErCXrel8
E1D32ELOOPZrCXrel8....z...Decrement count; Jump short if count!=0 and ZF=1
LOOPErCXrel8
E2D32ELOOPrCXrel8Decrement count; Jump short if count!=0
E3D32EJECXZrel8ECXJump short if rCX register is 0
JRCXZrel8RCX
E4f1INALimm8Input from Port
E5f1INeAXimm8Input from Port
E6f1OUTimm8ALOutput to Port
E7f1OUTimm8eAXOutput to Port
E8D32CALLrel16/32Call Procedure
E9D32JMPrel16/32Jump
EAEinvalidInvalid Instruction in 64-Bit Mode
EBJMPrel8Jump
ECf1INALDXInput from Port
EDf1INeAXDXInput from Port
EEf1OUTDXALOutput to Port
EFf1OUTDXeAXOutput to Port
F0LOCKAssert LOCK# Signal Prefix
F1D4undefinedUndefined and Reserved; Does not Generate #UD
F1U10INT1eFlags..i.......i.......i.....Call to Interrupt Procedure
ICEBPeFlags
F2D11EREPNZrCX....z...Repeat String Operation Prefix
REPNErCX
F2U11EREPrCXRepeat String Operation Prefix
F2Mno mnemonicsse2Scalar Double-precision Prefix
F3D11EREPZrCX....z...Repeat String Operation Prefix
REPErCX
F3D11EREPrCXRepeat String Operation Prefix
F3Mno mnemonicsse1Scalar Single-precision Prefix
F40HLTHalt
F5CMC.......c.......c.......cComplement Carry Flag
F60TESTr/m8imm8o..szapco..sz.pc.....a..o......cLogical Compare
F61U12TESTr/m8imm8o..szapco..sz.pc.....a..o......cLogical Compare
F62NOTr/m8One's Complement Negation
F63NEGr/m8o..szapco..szapcTwo's Complement Negation
F64MULAXALr/m8o..szapco......c...szap.Unsigned Multiply
F65IMULAXALr/m8o..szapco......c...szap.Signed Multiply
F66DIVALAHAXr/m8o..szapco..szapcUnsigned Divide
F67IDIVALAHAXr/m8o..szapco..szapcSigned Divide
F70TESTr/m16/32/64imm16/32/64o..szapco..sz.pc.....a..o......cLogical Compare
F71U12TESTr/m16/32/64imm16/32/64o..szapco..sz.pc.....a..o......cLogical Compare
F72NOTr/m16/32/64One's Complement Negation
F73NEGr/m16/32/64o..szapco..szapcTwo's Complement Negation
F74MULrDXrAXr/m16/32/64o..szapco......c...szap.Unsigned Multiply
F75IMULrDXrAXr/m16/32/64o..szapco......c...szap.Signed Multiply
F76DIVrDXrAXr/m16/32/64o..szapco..szapcUnsigned Divide
F77IDIVrDXrAXr/m16/32/64o..szapco..szapcSigned Divide
F8CLC.......c.......c.......cClear Carry Flag
F9STC.......c.......c.......CSet Carry Flag
FAf1CLI..i.......i.......i.....Clear Interrupt Flag
FBf1STI..i.......i.......I.....Set Interrupt Flag
FCCLD.d.......d.......d......Clear Direction Flag
FDSTD.d.......d.......D......Set Direction Flag
FE0INCr/m8o..szap.o..szap.Increment by 1
FE1DECr/m8o..szap.o..szap.Decrement by 1
FF0INCr/m16/32/64o..szap.o..szap.Increment by 1
FF1DECr/m16/32/64o..szap.o..szap.Decrement by 1
FF2CALLr/m16/32Call Procedure
FF2D32ECALLr/m64Call Procedure
FF3D13CALLFm16:16/32/64Call Procedure
FF4JMPr/m16/32Jump
FF4D32EJMPr/m64Jump
FF5D13JMPFm16:16/32/64Jump
FF6PUSHr/m16/32Push Word, Doubleword or Quadword Onto the Stack
FF6EPUSHr/m64/16Push Word, Doubleword or Quadword Onto the Stack
pf0Fposooprocstmrlxmnemonicop1op2op3op4iexttested fmodif fdef fundef ff valuesdescription, notes                                        
0F000PSLDTm16LDTRStore Local Descriptor Table Register
SLDTr16/32/64LDTR
0F001PSTRm16TRStore Task Register
STRr16/32/64TR
0F002P0LLDTLDTRr/m16Load Local Descriptor Table Register
0F003P0LTRTRr/m16Load Task Register
0F004PVERRr/m16....z.......z...Verify a Segment for Reading
0F005PVERWr/m16....z.......z...Verify a Segment for Writing
0F010SGDTmGDTRStore Global Descriptor Table Register
0F01C10D33P0VMCALLvmxo..szapco..szapcCall to VM Monitor
0F01C20D33P0VMLAUNCHvmxo..szapco..szapcLaunch Virtual Machine
0F01C30D33P0VMRESUMEvmxo..szapco..szapcResume Virtual Machine
0F01C40D33P0VMXOFFvmxo..szapco..szapcLeave VMX Operation
0F011SIDTmIDTRStore Interrupt Descriptor Table Register
0F01C810MONITORm8ECXEDXsse3Set Up Monitor Address
0F01C910MWAITEAXECXsse3Monitor Wait
0F0120LGDTGDTRmLoad Global Descriptor Table Register
0F01D02C2++XGETBVEDXEAXECXXCRGet Value of Extended Control Register
0F01D12C2++0XSETBVXCRECXEDXEAXSet Extended Control Register
0F0130LIDTIDTRmLoad Interrupt Descriptor Table Register
0F014D14SMSWm16MSWStore Machine Status Word
SMSWr16/32/64MSW
0F0160LMSWMSWr/m16Load Machine Status Word
0F0170INVLPGmInvalidate TLB Entry
0F01F87E0SWAPGSGSIA32_KERNEL_…Swap GS Base Register
0F01F97C7+f2RDTSCPEAXEDXECX...Read Time-Stamp Counter and Processor ID
0F02rPLARr16/32/64m16....z.......z...Load Access Rights Byte
LARr16/32/64r16/32
0F03rPLSLr16/32/64m16....z.......z...Load Segment Limit
LSLr16/32/64r16/32
0F05D15ESYSCALLRCXR11SS...Fast System Call
0F060CLTSCR0Clear Task-Switched Flag in CR0
0F07E0SYSRETSSEFlagsR11...Return From Fast System Call
0F080INVDInvalidate Internal Caches
0F090WBINVDWrite Back and Invalidate Cache
0F0BUD2Undefined Instruction
0F0DM16NOPr/m16/32No Operation
0F10rMOVUPSxmmxmm/m128sse1Move Unaligned Packed Single-FP Values
F30F10rMOVSSxmmxmm/m32sse1Move Scalar Single-FP Values
660F10rMOVUPDxmmxmm/m128sse2Move Unaligned Packed Double-FP Value
F20F10rMOVSDxmmxmm/m64sse2Move Scalar Double-FP Value
0F11rMOVUPSxmm/m128xmmsse1Move Unaligned Packed Single-FP Values
F30F11rMOVSSxmm/m32xmmsse1Move Scalar Single-FP Values
660F11rMOVUPDxmm/m128xmmsse2Move Unaligned Packed Double-FP Values
F20F11rMOVSDxmm/m64xmmsse2Move Scalar Double-FP Value
0F12rMOVHLPSxmmxmmsse1Move Packed Single-FP Values High to Low
0F12rMOVLPSxmmm64sse1Move Low Packed Single-FP Values
660F12rMOVLPDxmmm64sse2Move Low Packed Double-FP Value
F20F12rMOVDDUPxmmxmm/m64sse3Move One Double-FP and Duplicate
F30F12rMOVSLDUPxmmxmm/m64sse3Move Packed Single-FP Low and Duplicate
0F13rMOVLPSm64xmmsse1Move Low Packed Single-FP Values
660F13rMOVLPDm64xmmsse2Move Low Packed Double-FP Value
0F14rUNPCKLPSxmmxmm/m64sse1Unpack and Interleave Low Packed Single-FP Values
660F14rUNPCKLPDxmmxmm/m128sse2Unpack and Interleave Low Packed Double-FP Values
0F15rUNPCKHPSxmmxmm/m64sse1Unpack and Interleave High Packed Single-FP Values
660F15rUNPCKHPDxmmxmm/m128sse2Unpack and Interleave High Packed Double-FP Values
0F16rMOVLHPSxmmxmmsse1Move Packed Single-FP Values Low to High
0F16rMOVHPSxmmm64sse1Move High Packed Single-FP Values
660F16rMOVHPDxmmm64sse2Move High Packed Double-FP Value
F30F16rMOVSHDUPxmmxmm/m64sse3Move Packed Single-FP High and Duplicate
0F17rMOVHPSm64xmmsse1Move High Packed Single-FP Values
660F17rMOVHPDm64xmmsse2Move High Packed Double-FP Value
0F180PREFETCHNTAm8sse1Prefetch Data Into Caches
0F181PREFETCHT0m8sse1Prefetch Data Into Caches
0F182PREFETCHT1m8sse1Prefetch Data Into Caches
0F183PREFETCHT2m8sse1Prefetch Data Into Caches
0F184M17HINT_NOPr/m16/32Hintable NOP
0F185M17HINT_NOPr/m16/32Hintable NOP
0F186M17HINT_NOPr/m16/32Hintable NOP
0F187M17HINT_NOPr/m16/32Hintable NOP
0F19M17HINT_NOPr/m16/32Hintable NOP
0F1AM17HINT_NOPr/m16/32Hintable NOP
0F1BM17HINT_NOPr/m16/32Hintable NOP
0F1CM17HINT_NOPr/m16/32Hintable NOP
0F1DM17HINT_NOPr/m16/32Hintable NOP
0F1EM17HINT_NOPr/m16/32Hintable NOP
0F1F0NOPr/m16/32No Operation
0F1F1M17HINT_NOPr/m16/32Hintable NOP
0F1F2M17HINT_NOPr/m16/32Hintable NOP
0F1F3M17HINT_NOPr/m16/32Hintable NOP
0F1F4M17HINT_NOPr/m16/32Hintable NOP
0F1F5M17HINT_NOPr/m16/32Hintable NOP
0F1F6M17HINT_NOPr/m16/32Hintable NOP
0F1F7M17HINT_NOPr/m16/32Hintable NOP
0F20rE0MOVr64CRno..szapco..szapcMove to/from Control Registers
0F20rU18E0MOVr64CRno..szapco..szapcMove to/from Control Registers
0F21rE0MOVr64DRno..szapco..szapcMove to/from Debug Registers
0F21rU18E0MOVr64DRno..szapco..szapcMove to/from Debug Registers
0F22rE0MOVCRnr64o..szapco..szapcMove to/from Control Registers
0F22rU18E0MOVCRnr64o..szapco..szapcMove to/from Control Registers
0F23rE0MOVDRnr64o..szapco..szapcMove to/from Debug Registers
0F23rU18E0MOVDRnr64o..szapco..szapcMove to/from Debug Registers
0F28rMOVAPSxmmxmm/m128sse1Move Aligned Packed Single-FP Values
660F28rMOVAPDxmmxmm/m128sse2Move Aligned Packed Double-FP Values
0F29rMOVAPSxmm/m128xmmsse1Move Aligned Packed Single-FP Values
660F29rMOVAPDxmm/m128xmmsse2Move Aligned Packed Double-FP Values
0F2ArCVTPI2PSxmmmm/m64sse1Convert Packed DW Integers to Single-FP Values
F30F2ArCVTSI2SSxmmr/m32/64sse1Convert DW Integer to Scalar Single-FP Value
660F2ArCVTPI2PDxmmmm/m64sse2Convert Packed DW Integers to Double-FP Values
F20F2ArCVTSI2SDxmmr/m32/64sse2Convert DW Integer to Scalar Double-FP Value
0F2BrMOVNTPSm128xmmsse1Store Packed Single-FP Values Using Non-Temporal Hint
660F2BrMOVNTPDm128xmmsse2Store Packed Double-FP Values Using Non-Temporal Hint
0F2CrCVTTPS2PImmxmm/m64sse1Convert with Trunc. Packed Single-FP Values to DW Integers
F30F2CrCVTTSS2SIr32/64xmm/m32sse1Convert with Trunc. Scalar Single-FP Value to DW Integer
660F2CrCVTTPD2PImmxmm/m128sse2Convert with Trunc. Packed Double-FP Values to DW Integers
F20F2CrCVTTSD2SIr32/64xmm/m64sse2Conv. with Trunc. Scalar Double-FP Value to Signed DW Int
0F2DrCVTPS2PImmxmm/m64sse1Convert Packed Single-FP Values to DW Integers
F30F2DrCVTSS2SIr32/64xmm/m32sse1Convert Scalar Single-FP Value to DW Integer
660F2DrCVTPD2PImmxmm/m128sse2Convert Packed Double-FP Values to DW Integers
F20F2DrCVTSD2SIr32/64xmm/m64sse2Convert Scalar Double-FP Value to DW Integer
0F2ErUCOMISSxmmxmm/m32sse1....z.pc....z.pcUnordered Compare Scalar Single-FP Values and Set EFLAGS
660F2ErUCOMISDxmmxmm/m64sse2....z.pc....z.pcUnordered Compare Scalar Double-FP Values and Set EFLAGS
0F2FrCOMISSxmmxmm/m32sse1....z.pc....z.pcCompare Scalar Ordered Single-FP Values and Set EFLAGS
660F2FrCOMISDxmmxmm/m64sse2....z.pc....z.pcCompare Scalar Ordered Double-FP Values and Set EFLAGS
0F300WRMSRMSRrCXrAXrDXWrite to Model Specific Register
0F31f2RDTSCEAXEDXIA32_TIME_S…Read Time-Stamp Counter
0F320RDMSRrAXrDXrCXMSRRead from Model Specific Register
0F33f3RDPMCEAXEDXPMCRead Performance-Monitoring Counters
0F34D19ESYSENTERSSRSPIA32_SYSENT….....i.......i.......i.....Fast System Call
0F35D20P0SYSEXITSSeSPIA32_SYSENT…...Fast Return from Fast System Call
0F37C2++D21GETSECEAXsmxGETSEC Leaf Functions
660F3880rC2++D33E0INVEPTr64m128vmxo..szapco..szapcInvalidate Translations Derived from EPT
660F3881rC2++D33E0INVVPIDr64m128vmxo..szapco..szapcInvalidate Translations Based on VPID
0F38F0rC2++MOVBEr16/32/64m16/32/64Move Data After Swapping Bytes
F20F38F0rC2++D34CRC32r32/64r/m8sse42Accumulate CRC32 Value
0F38F1rC2++MOVBEm16/32/64r16/32/64Move Data After Swapping Bytes
F20F38F1rC2++D34CRC32r32/64r/m16/32/64sse42Accumulate CRC32 Value
660F3A08rC2++D34ROUNDPSxmmxmm/m128imm8sse41Round Packed Single-FP Values
660F3A09rC2++D34ROUNDPDxmmxmm/m128imm8sse41Round Packed Double-FP Values
660F3A0ArC2++D34ROUNDSSxmmxmm/m32imm8sse41Round Scalar Single-FP Values
660F3A0BrC2++D34ROUNDSDxmmxmm/m64imm8sse41Round Scalar Double-FP Values
660F3A0CrC2++D34BLENDPSxmmxmm/m128imm8sse41Blend Packed Single-FP Values
660F3A0DrC2++D34BLENDPDxmmxmm/m128imm8sse41Blend Packed Double-FP Values
660F3A0ErC2++D34PBLENDWxmmxmm/m128imm8sse41Blend Packed Words
0F3A0FrC2+PALIGNRmmmm/m64ssse3Packed Align Right
660F3A0FrC2+PALIGNRxmmxmm/m128ssse3Packed Align Right
660F3A14rC2++D34PEXTRBm8xmmimm8sse41Extract Byte
PEXTRBr32/64xmmimm8
660F3A15rC2++D34PEXTRWm16xmmimm8sse41Extract Word
PEXTRWr32/64xmmimm8
660F3A16rC2++D34PEXTRDr/m32xmmimm8sse41Extract Dword/Qword
PEXTRQr/m64xmmimm8
660F3A17rC2++D34EXTRACTPSr/m32xmmimm8sse41Extract Packed Single-FP Value
660F3A20rC2++D34PINSRBxmmm8imm8sse41Insert Byte
PINSRBxmmr32/64imm8
660F3A21rC2++D34INSERTPSxmmxmmimm8sse41Insert Packed Single-FP Value
INSERTPSxmmm32imm8
660F3A22rC2++D34PINSRDxmmr/m32imm8sse41Insert Dword/Qword
PINSRQxmmr/m64imm8
660F3A40rC2++D34DPPSxmmxmm/m128sse41Dot Product of Packed Single-FP Values
660F3A41rC2++D34DPPDxmmxmm/m128sse41Dot Product of Packed Double-FP Values
660F3A42rC2++D34MPSADBWxmmxmm/m128imm8sse41Compute Multiple Packed Sums of Absolute Difference
660F3A60rC2++D34PCMPESTRMXMM0xmmxmm/m128...sse42o..szapco..szapc.....ap.Packed Compare Explicit Length Strings, Return Mask
660F3A61rC2++D34PCMPESTRIrCXxmmxmm/m128...sse42o..szapco..szapc.....ap.Packed Compare Explicit Length Strings, Return Index
660F3A62rC2++D34PCMPISTRMXMM0xmmxmm/m128imm8sse42o..szapco..szapc.....ap.Packed Compare Implicit Length Strings, Return Mask
660F3A63rC2++D34PCMPISTRIrCXxmmxmm/m128imm8sse42o..szapco..szapc.....ap.Packed Compare Implicit Length Strings, Return Index
0F40rD23CMOVOr16/32/64r/m16/32/64o.......Conditional Move - overflow (OF=1)
0F41rD23CMOVNOr16/32/64r/m16/32/64o.......Conditional Move - not overflow (OF=0)
0F42rD23CMOVBr16/32/64r/m16/32/64.......cConditional Move - below/not above or equal/carry (CF=1)
CMOVNAEr16/32/64r/m16/32/64
CMOVCr16/32/64r/m16/32/64
0F43rD23CMOVNBr16/32/64r/m16/32/64.......cConditional Move - not below/above or equal/not carry (CF=0)
CMOVAEr16/32/64r/m16/32/64
CMOVNCr16/32/64r/m16/32/64
0F44rD23CMOVZr16/32/64r/m16/32/64....z...Conditional Move - zero/equal (ZF=0)
CMOVEr16/32/64r/m16/32/64
0F45rD23CMOVNZr16/32/64r/m16/32/64....z...Conditional Move - not zero/not equal (ZF=1)
CMOVNEr16/32/64r/m16/32/64
0F46rD23CMOVBEr16/32/64r/m16/32/64....z..cConditional Move - below or equal/not above (CF=1 AND ZF=1)
CMOVNAr16/32/64r/m16/32/64
0F47rD23CMOVNBEr16/32/64r/m16/32/64....z..cConditional Move - not below or equal/above (CF=0 AND ZF=0)
CMOVAr16/32/64r/m16/32/64
0F48rD23CMOVSr16/32/64r/m16/32/64...s....Conditional Move - sign (SF=1)
0F49rD23CMOVNSr16/32/64r/m16/32/64...s....Conditional Move - not sign (SF=0)
0F4ArD23CMOVPr16/32/64r/m16/32/64......p.Conditional Move - parity/parity even (PF=1)
CMOVPEr16/32/64r/m16/32/64
0F4BrD23CMOVNPr16/32/64r/m16/32/64......p.Conditional Move - not parity/parity odd
CMOVPOr16/32/64r/m16/32/64
0F4CrD23CMOVLr16/32/64r/m16/32/64o..s....Conditional Move - less/not greater (SF!=OF)
CMOVNGEr16/32/64r/m16/32/64
0F4DrD23CMOVNLr16/32/64r/m16/32/64o..s....Conditional Move - not less/greater or equal (SF=OF)
CMOVGEr16/32/64r/m16/32/64
0F4ErD23CMOVLEr16/32/64r/m16/32/64o..sz...Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
CMOVNGr16/32/64r/m16/32/64
0F4FrD23CMOVNLEr16/32/64r/m16/32/64o..sz...Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
CMOVGr16/32/64r/m16/32/64
0F50rMOVMSKPSr32/64xmmsse1Extract Packed Single-FP Sign Mask
660F50rMOVMSKPDr32/64xmmsse2Extract Packed Double-FP Sign Mask
0F51rSQRTPSxmmxmm/m128sse1Compute Square Roots of Packed Single-FP Values
F30F51rSQRTSSxmmxmm/m32sse1Compute Square Root of Scalar Single-FP Value
660F51rSQRTPDxmmxmm/m128sse2Compute Square Roots of Packed Double-FP Values
F20F51rSQRTSDxmmxmm/m64sse2Compute Square Root of Scalar Double-FP Value
0F52rRSQRTPSxmmxmm/m128sse1Compute Recipr. of Square Roots of Packed Single-FP Values
F30F52rRSQRTSSxmmxmm/m32sse1Compute Recipr. of Square Root of Scalar Single-FP Value
0F53rRCPPSxmmxmm/m128sse1Compute Reciprocals of Packed Single-FP Values
F30F53rRCPSSxmmxmm/m32sse1Compute Reciprocal of Scalar Single-FP Values
0F54rANDPSxmmxmm/m128sse1Bitwise Logical AND of Packed Single-FP Values
660F54rANDPDxmmxmm/m128sse2Bitwise Logical AND of Packed Double-FP Values
0F55rANDNPSxmmxmm/m128sse1Bitwise Logical AND NOT of Packed Single-FP Values
660F55rANDNPDxmmxmm/m128sse2Bitwise Logical AND NOT of Packed Double-FP Values
0F56rORPSxmmxmm/m128sse1Bitwise Logical OR of Single-FP Values
660F56rORPDxmmxmm/m128sse2Bitwise Logical OR of Double-FP Values
0F57rXORPSxmmxmm/m128sse1Bitwise Logical XOR for Single-FP Values
660F57rXORPDxmmxmm/m128sse2Bitwise Logical XOR for Double-FP Values
0F58rADDPSxmmxmm/m128sse1Add Packed Single-FP Values
F30F58rADDSSxmmxmm/m32sse1Add Scalar Single-FP Values
660F58rADDPDxmmxmm/m128sse2Add Packed Double-FP Values
F20F58rADDSDxmmxmm/m64sse2Add Scalar Double-FP Values
0F59rMULPSxmmxmm/m128sse1Multiply Packed Single-FP Values
F30F59rMULSSxmmxmm/m32sse1Multiply Scalar Single-FP Value
660F59rMULPDxmmxmm/m128sse2Multiply Packed Double-FP Values
F20F59rMULSDxmmxmm/m64sse2Multiply Scalar Double-FP Values
0F5ArCVTPS2PDxmmxmm/m128sse2Convert Packed Single-FP Values to Double-FP Values
660F5ArCVTPD2PSxmmxmm/m128sse2Convert Packed Double-FP Values to Single-FP Values
F30F5ArCVTSS2SDxmmxmm/m32sse2Convert Scalar Single-FP Value to Scalar Double-FP Value
F20F5ArCVTSD2SSxmmxmm/m64sse2Convert Scalar Double-FP Value to Scalar Single-FP Value
0F5BrCVTDQ2PSxmmxmm/m128sse2Convert Packed DW Integers to Single-FP Values
660F5BrCVTPS2DQxmmxmm/m128sse2Convert Packed Single-FP Values to DW Integers
F30F5BrCVTTPS2DQxmmxmm/m128sse2Convert with Trunc. Packed Single-FP Values to DW Integers
0F5CrSUBPSxmmxmm/m128sse1Subtract Packed Single-FP Values
F30F5CrSUBSSxmmxmm/m32sse1Subtract Scalar Single-FP Values
660F5CrSUBPDxmmxmm/m128sse2Subtract Packed Double-FP Values
F20F5CrSUBSDxmmxmm/m64sse2Subtract Scalar Double-FP Values
0F5DrMINPSxmmxmm/m128sse1Return Minimum Packed Single-FP Values
F30F5DrMINSSxmmxmm/m32sse1Return Minimum Scalar Single-FP Value
660F5DrMINPDxmmxmm/m128sse2Return Minimum Packed Double-FP Values
F20F5DrMINSDxmmxmm/m64sse2Return Minimum Scalar Double-FP Value
0F5ErDIVPSxmmxmm/m128sse1Divide Packed Single-FP Values
F30F5ErDIVSSxmmxmm/m32sse1Divide Scalar Single-FP Values
660F5ErDIVPDxmmxmm/m128sse2Divide Packed Double-FP Values
F20F5ErDIVSDxmmxmm/m64sse2Divide Scalar Double-FP Values
0F5FrMAXPSxmmxmm/m128sse1Return Maximum Packed Single-FP Values
F30F5FrMAXSSxmmxmm/m32sse1Return Maximum Scalar Single-FP Value
660F5FrMAXPDxmmxmm/m128sse2Return Maximum Packed Double-FP Values
F20F5FrMAXSDxmmxmm/m64sse2Return Maximum Scalar Double-FP Value
0F60rPUNPCKLBWmmmm/m64mmxUnpack Low Data
660F60rPUNPCKLBWxmmxmm/m128sse2Unpack Low Data
0F61rPUNPCKLWDmmmm/m64mmxUnpack Low Data
660F61rPUNPCKLWDxmmxmm/m128sse2Unpack Low Data
0F62rPUNPCKLDQmmmm/m64mmxUnpack Low Data
660F62rPUNPCKLDQxmmxmm/m128sse2Unpack Low Data
0F63rPACKSSWBmmmm/m64mmxPack with Signed Saturation
660F63rPACKSSWBxmmxmm/m128sse2Pack with Signed Saturation
0F64rPCMPGTBmmmm/m64mmxCompare Packed Signed Integers for Greater Than
660F64rPCMPGTBxmmxmm/m128sse2Compare Packed Signed Integers for Greater Than
0F65rPCMPGTWmmmm/m64mmxCompare Packed Signed Integers for Greater Than
660F65rPCMPGTWxmmxmm/m128sse2Compare Packed Signed Integers for Greater Than
0F66rPCMPGTDmmmm/m64mmxCompare Packed Signed Integers for Greater Than
660F66rPCMPGTDxmmxmm/m128sse2Compare Packed Signed Integers for Greater Than
0F67rPACKUSWBmmmm/m64mmxPack with Unsigned Saturation
660F67rPACKUSWBxmmxmm/m128sse2Pack with Unsigned Saturation
0F68rPUNPCKHBWmmmm/m64mmxUnpack High Data
660F68rPUNPCKHBWxmmxmm/m128sse2Unpack High Data
0F69rPUNPCKHWDmmmm/m64mmxUnpack High Data
660F69rPUNPCKHWDxmmxmm/m128sse2Unpack High Data
0F6ArPUNPCKHDQmmmm/m64mmxUnpack High Data
660F6ArPUNPCKHDQxmmxmm/m128sse2Unpack High Data
0F6BrPACKSSDWmmmm/m64mmxPack with Signed Saturation
660F6BrPACKSSDWxmmxmm/m128sse2Pack with Signed Saturation
660F6CrPUNPCKLQDQxmmxmm/m128sse2Unpack Low Data
660F6DrPUNPCKHQDQxmmxmm/m128sse2Unpack High Data
0F6ErD22EMOVDmmr/m32mmxMove Doubleword/Quadword
MOVQmmr/m64
660F6ErD22EMOVDxmmr/m32sse2Move Doubleword/Quadword
MOVQxmmr/m64
0F6FrMOVQmmmm/m64mmxMove Quadword
660F6FrMOVDQAxmmxmm/m128sse2Move Aligned Double Quadword
F30F6FrMOVDQUxmmxmm/m128sse2Move Unaligned Double Quadword
0F70rPSHUFWmmmm/m64imm8sse1Shuffle Packed Words
F20F70rPSHUFLWxmmxmm/m128imm8sse2Shuffle Packed Low Words
F30F70rPSHUFHWxmmxmm/m128imm8sse2Shuffle Packed High Words
660F70rPSHUFDxmmxmm/m128imm8sse2Shuffle Packed Doublewords
0F712PSRLWmmimm8mmxShift Packed Data Right Logical
660F712PSRLWxmmimm8sse2Shift Packed Data Right Logical
0F714PSRAWmmimm8mmxShift Packed Data Right Arithmetic
660F714PSRAWxmmimm8sse2Shift Packed Data Right Arithmetic
0F716PSLLWmmimm8mmxShift Packed Data Left Logical
660F716PSLLWxmmimm8sse2Shift Packed Data Left Logical
0F722PSRLDmmimm8mmxShift Double Quadword Right Logical
660F722PSRLDxmmimm8sse2Shift Double Quadword Right Logical
0F724PSRADmmimm8mmxShift Packed Data Right Arithmetic
660F724PSRADxmmimm8sse2Shift Packed Data Right Arithmetic
0F726PSLLDmmimm8mmxShift Packed Data Left Logical
660F726PSLLDxmmimm8sse2Shift Packed Data Left Logical
0F732PSRLQmmimm8mmxShift Packed Data Right Logical
660F732PSRLQxmmimm8sse2Shift Packed Data Right Logical
660F733PSRLDQxmmimm8sse2Shift Double Quadword Right Logical
0F736PSLLQmmimm8mmxShift Packed Data Left Logical
660F736PSLLQxmmimm8sse2Shift Packed Data Left Logical
660F737PSLLDQxmmimm8sse2Shift Double Quadword Left Logical
0F74rPCMPEQBmmmm/m64mmxCompare Packed Data for Equal
660F74rPCMPEQBxmmxmm/m128sse2Compare Packed Data for Equal
0F75rPCMPEQWmmmm/m64mmxCompare Packed Data for Equal
660F75rPCMPEQWxmmxmm/m128sse2Compare Packed Data for Equal
0F76rPCMPEQDmmmm/m64mmxCompare Packed Data for Equal
660F76rPCMPEQDxmmxmm/m128sse2Compare Packed Data for Equal
0F77EMMSmmxEmpty MMX Technology State
0F78rD33E0VMREADr/m64r64vmxo..szapco..szapcRead Field from Virtual-Machine Control Structure
0F79rD33E0VMWRITEr64r/m64vmxo..szapco..szapcWrite Field to Virtual-Machine Control Structure
660F7CrHADDPDxmmxmm/m128sse3Packed Double-FP Horizontal Add
F20F7CrHADDPSxmmxmm/m128sse3Packed Single-FP Horizontal Add
660F7DrHSUBPDxmmxmm/m128sse3Packed Double-FP Horizontal Subtract
F20F7DrHSUBPSxmmxmm/m128sse3Packed Single-FP Horizontal Subtract
0F7ErD22EMOVDr/m32mmmmxMove Doubleword/Quadword
MOVQr/m64mm
660F7ErD22EMOVDr/m32xmmsse2Move Doubleword/Quadword
MOVQr/m64r/m
F30F7ErMOVQxmmxmm/m64sse2Move Quadword
0F7FrMOVQmm/m64mmmmxMove Quadword
660F7FrMOVDQAxmm/m128xmmsse2Move Aligned Double Quadword
F30F7FrMOVDQUxmm/m128xmmsse2Move Unaligned Double Quadword
0F80D32JOrel16/32o.......Jump short if overflow (OF=1)
0F81D32JNOrel16/32o.......Jump short if not overflow (OF=0)
0F82D32JBrel16/32.......cJump short if below/not above or equal/carry (CF=1)
JNAErel16/32
JCrel16/32
0F83D32JNBrel16/32.......cJump short if not below/above or equal/not carry (CF=0)
JAErel16/32
JNCrel16/32
0F84D32JZrel16/32....z...Jump short if zero/equal (ZF=0)
JErel16/32
0F85D32JNZrel16/32....z...Jump short if not zero/not equal (ZF=1)
JNErel16/32
0F86D32JBErel16/32....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNArel16/32
0F87D32JNBErel16/32....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JArel16/32
0F88D32JSrel16/32...s....Jump short if sign (SF=1)
0F89D32JNSrel16/32...s....Jump short if not sign (SF=0)
0F8AD32JPrel16/32......p.Jump short if parity/parity even (PF=1)
JPErel16/32
0F8BD32JNPrel16/32......p.Jump short if not parity/parity odd
JPOrel16/32
0F8CD32JLrel16/32o..s....Jump short if less/not greater (SF!=OF)
JNGErel16/32
0F8DD32JNLrel16/32o..s....Jump short if not less/greater or equal (SF=OF)
JGErel16/32
0F8ED32JLErel16/32o..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNGrel16/32
0F8FD32JNLErel16/32o..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JGrel16/32
0F900D24SETOr/m8o.......Set Byte on Condition - overflow (OF=1)
0F910D24SETNOr/m8o.......Set Byte on Condition - not overflow (OF=0)
0F920D24SETBr/m8.......cSet Byte on Condition - below/not above or equal/carry (CF=1)
SETNAEr/m8
SETCr/m8
0F930D24SETNBr/m8.......cSet Byte on Condition - not below/above or equal/not carry (CF=0)
SETAEr/m8
SETNCr/m8
0F940D24SETZr/m8....z...Set Byte on Condition - zero/equal (ZF=0)
SETEr/m8
0F950D24SETNZr/m8....z...Set Byte on Condition - not zero/not equal (ZF=1)
SETNEr/m8
0F960D24SETBEr/m8....z..cSet Byte on Condition - below or equal/not above (CF=1 AND ZF=1)
SETNAr/m8
0F970D24SETNBEr/m8....z..cSet Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
SETAr/m8
0F980D24SETSr/m8...s....Set Byte on Condition - sign (SF=1)
0F990D24SETNSr/m8...s....Set Byte on Condition - not sign (SF=0)
0F9A0D24SETPr/m8......p.Set Byte on Condition - parity/parity even (PF=1)
SETPEr/m8
0F9B0D24SETNPr/m8......p.Set Byte on Condition - not parity/parity odd
SETPOr/m8
0F9C0D24SETLr/m8o..s....Set Byte on Condition - less/not greater (SF!=OF)
SETNGEr/m8
0F9D0D24SETNLr/m8o..s....Set Byte on Condition - not less/greater or equal (SF=OF)
SETGEr/m8
0F9E0D24SETLEr/m8o..sz...Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
SETNGr/m8
0F9F0D24SETNLEr/m8o..sz...Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
SETGr/m8
0FA0PUSHFSPush Word, Doubleword or Quadword Onto the Stack
0FA1POPFSPop a Value from the Stack
0FA2CPUIDIA32_BIOS_SIG…EAXECX...CPU Identification
0FA3rBTr/m16/32/64r16/32/64o..szapc.......co..szap.Bit Test
0FA4rSHLDr/m16/32/64r16/32/64imm8o..szapco..sz.pco....a.cDouble Precision Shift Left
0FA5rSHLDr/m16/32/64r16/32/64CLo..szapco..sz.pco....a.cDouble Precision Shift Left
0FA8PUSHGSPush Word, Doubleword or Quadword Onto the Stack
0FA9POPGSPop a Value from the Stack
0FAASRSMFlagsResume from System Management Mode
0FABrLBTSr/m16/32/64r16/32/64o..szapc.......co..szap.Bit Test and Set
0FACrSHRDr/m16/32/64r16/32/64imm8o..szapco..sz.pco....a.cDouble Precision Shift Right
0FADrSHRDr/m16/32/64r16/32/64CLo..szapco..sz.pco....a.cDouble Precision Shift Right
0FAE0FXSAVEm512STST1...Save x87 FPU, MMX, XMM, and MXCSR State
0FAE0EFXSAVEm512STST1...Save x87 FPU, MMX, XMM, and MXCSR State
0FAE1FXRSTORSTST1ST2...Restore x87 FPU, MMX, XMM, and MXCSR State
0FAE1EFXRSTORSTST1ST2...Restore x87 FPU, MMX, XMM, and MXCSR State
0FAE2LDMXCSRm32sse1Load MXCSR Register
0FAE3STMXCSRm32sse1Store MXCSR Register State
0FAE4C2++XSAVEmEDXEAX...Save Processor Extended States
0FAE4C2++EXSAVEmEDXEAX...Save Processor Extended States
0FAE5LFENCEsse2Load Fence
0FAE5C2++EXRSTORSTST1ST2...Restore Processor Extended States
0FAE6MFENCEsse2Memory Fence
0FAE7SFENCEsse1Store Fence
0FAE7CLFLUSHm8sse2Flush Cache Line
0FAFrIMULr16/32/64r/m16/32/64o..szapco......c...szap.Signed Multiply
0FB0rD25LCMPXCHGr/m8ALr8o..szapco..szapcCompare and Exchange
0FB1rD25LCMPXCHGr/m16/32/64rAXr16/32/64o..szapco..szapcCompare and Exchange
0FB2rD26LSSSSr16/32/64m16:16/32/64Load Far Pointer
0FB3rLBTRr/m16/32/64r16/32/64o..szapc.......co..szap.Bit Test and Reset
0FB4rD26LFSFSr16/32/64m16:16/32/64Load Far Pointer
0FB5rD26LGSGSr16/32/64m16:16/32/64Load Far Pointer
0FB6rMOVZXr16/32/64r/m8Move with Zero-Extend
0FB7rMOVZXr16/32/64r/m16Move with Zero-Extend
F30FB8rC2++POPCNTr16/32/64r/m16/32/64o..szapco..s.apcBit Population Count
0FB9rM27UDrr/mUndefined Instruction
0FBA4BTr/m16/32/64imm8o..szapc.......co..szap.Bit Test
0FBA5LBTSr/m16/32/64imm8o..szapc.......co..szap.Bit Test and Set
0FBA6LBTRr/m16/32/64imm8o..szapc.......co..szap.Bit Test and Reset
0FBA7LBTCr/m16/32/64imm8o..szapc.......co..szap.Bit Test and Complement
0FBBrLBTCr/m16/32/64r16/32/64o..szapc.......co..szap.Bit Test and Complement
0FBCrD28BSFr16/32/64r/m16/32/64o..szapc....z...o..s.apcBit Scan Forward
0FBDrD28BSRr16/32/64r/m16/32/64o..szapc....z...o..s.apcBit Scan Reverse
0FBErMOVSXr16/32/64r/m8Move with Sign-Extension
0FBFrMOVSXr16/32/64r/m16Move with Sign-Extension
0FC0rLXADDr/m8r8o..szapco..szapcExchange and Add
0FC1rLXADDr/m16/32/64r16/32/64o..szapco..szapcExchange and Add
0FC2rCMPPSxmmxmm/m128imm8sse1Compare Packed Single-FP Values
F30FC2rCMPSSxmmxmm/m32imm8sse1Compare Scalar Single-FP Values
660FC2rCMPPDxmmxmm/m128imm8sse2Compare Packed Double-FP Values
F20FC2rCMPSDxmmxmm/m64imm8sse2Compare Scalar Double-FP Values
0FC3rMOVNTIm32/64r32/64sse2Store Doubleword Using Non-Temporal Hint
0FC4rPINSRWmmr32/64imm8sse1Insert Word
PINSRWmmm16imm8
660FC4rPINSRWxmmr32/64imm8sse1Insert Word
PINSRWxmmm16imm8
0FC5rPEXTRWr32/64mmimm8sse1Extract Word
660FC5rPEXTRWr32/64xmmimm8sse1Extract Word
0FC6rSHUFPSxmmxmm/m128imm8sse1Shuffle Packed Single-FP Values
660FC6rSHUFPDxmmxmm/m128imm8sse2Shuffle Packed Double-FP Values
0FC71D29LCMPXCHG8Bm64EAXEDX.......z.......z...Compare and Exchange Bytes
0FC71D29ELCMPXCHG8Bm64EAXEDX.......z.......z...Compare and Exchange Bytes
CMPXCHG16Bm128RAXRDX...
0FC76D33P0VMPTRLDm64vmxo..szapco..szapcLoad Pointer to Virtual-Machine Control Structure
660FC76D33P0VMCLEARm64vmxo..szapco..szapcClear Virtual-Machine Control Structure
F30FC76D33P0VMXONm64vmxo..szapco..szapcEnter VMX Operation
0FC77D33P0VMPTRSTm64vmxo..szapco..szapcStore Pointer to Virtual-Machine Control Structure
0FC8+rD30BSWAPr16/32/64Byte Swap
660FD0rADDSUBPDxmmxmm/m128sse3Packed Double-FP Add/Subtract
F20FD0rADDSUBPSxmmxmm/m128sse3Packed Single-FP Add/Subtract
0FD1rPSRLWmmmm/m64mmxShift Packed Data Right Logical
660FD1rPSRLWxmmxmm/m128sse2Shift Packed Data Right Logical
0FD2rPSRLDmmmm/m64mmxShift Packed Data Right Logical
660FD2rPSRLDxmmxmm/m128sse2Shift Packed Data Right Logical
0FD3rPSRLQmmmm/m64mmxShift Packed Data Right Logical
660FD3rPSRLQxmmxmm/m128sse2Shift Packed Data Right Logical
0FD4rPADDQmmmm/m64sse2Add Packed Quadword Integers
660FD4rPADDQxmmxmm/m128sse2Add Packed Quadword Integers
0FD5rPMULLWmmmm/m64mmxMultiply Packed Signed Integers and Store Low Result
660FD5rPMULLWxmmxmm/m128sse2Multiply Packed Signed Integers and Store Low Result
660FD6rMOVQxmm/m64xmmsse2Move Quadword
F30FD6rMOVQ2DQxmmmmsse2Move Quadword from MMX Technology to XMM Register
F20FD6rMOVDQ2Qmmxmmsse2Move Quadword from XMM to MMX Technology Register
0FD7rPMOVMSKBr32/64mmsse1Move Byte Mask
660FD7rPMOVMSKBr32/64xmmsse1Move Byte Mask
0FD8rPSUBUSBmmmm/m64mmxSubtract Packed Unsigned Integers with Unsigned Saturation
660FD8rPSUBUSBxmmxmm/m128sse2Subtract Packed Unsigned Integers with Unsigned Saturation
0FD9rPSUBUSWmmmm/m64mmxSubtract Packed Unsigned Integers with Unsigned Saturation
660FD9rPSUBUSWxmmxmm/m128sse2Subtract Packed Unsigned Integers with Unsigned Saturation
0FDArPMINUBmmmm/m64sse1Minimum of Packed Unsigned Byte Integers
660FDArPMINUBxmmxmm/m128sse1Minimum of Packed Unsigned Byte Integers
0FDBrPANDmmmm/m64mmxLogical AND
660FDBrPANDxmmxmm/m128sse2Logical AND
0FDCrPADDUSBmmmm/m64mmxAdd Packed Unsigned Integers with Unsigned Saturation
660FDCrPADDUSBxmmxmm/m128sse2Add Packed Unsigned Integers with Unsigned Saturation
0FDDrPADDUSWmmmm/m64mmxAdd Packed Unsigned Integers with Unsigned Saturation
660FDDrPADDUSWxmmxmm/m128sse2Add Packed Unsigned Integers with Unsigned Saturation
0FDErPMAXUBmmmm/m64sse1Maximum of Packed Unsigned Byte Integers
660FDErPMAXUBxmmxmm/m128sse1Maximum of Packed Unsigned Byte Integers
0FDFrPANDNmmmm/m64mmxLogical AND NOT
660FDFrPANDNxmmxmm/m128sse2Logical AND NOT
0FE0rPAVGBmmmm/m64sse1Average Packed Integers
660FE0rPAVGBxmmxmm/m128sse1Average Packed Integers
0FE1rPSRAWmmmm/m64mmxShift Packed Data Right Arithmetic
660FE1rPSRAWxmmxmm/m128sse2Shift Packed Data Right Arithmetic
0FE2rPSRADmmmm/m64mmxShift Packed Data Right Arithmetic
660FE2rPSRADxmmxmm/m128sse2Shift Packed Data Right Arithmetic
0FE3rPAVGWmmmm/m64sse1Average Packed Integers
660FE3rPAVGWxmmxmm/m128sse1Average Packed Integers
0FE4rPMULHUWmmmm/m64sse1Multiply Packed Unsigned Integers and Store High Result
660FE4rPMULHUWxmmxmm/m128sse1Multiply Packed Unsigned Integers and Store High Result
0FE5rPMULHWmmmm/m64mmxMultiply Packed Signed Integers and Store High Result
660FE5rPMULHWxmmxmm/m128sse2Multiply Packed Signed Integers and Store High Result
F20FE6rCVTPD2DQxmmxmm/m128sse2Convert Packed Double-FP Values to DW Integers
660FE6rCVTTPD2DQxmmxmm/m128sse2Convert with Trunc. Packed Double-FP Values to DW Integers
F30FE6rCVTDQ2PDxmmxmm/m128sse2Convert Packed DW Integers to Double-FP Values
0FE7rMOVNTQm64mmsse1Store of Quadword Using Non-Temporal Hint
660FE7rMOVNTDQm128xmmsse2Store Double Quadword Using Non-Temporal Hint
0FE8rPSUBSBmmmm/m64mmxSubtract Packed Signed Integers with Signed Saturation
660FE8rPSUBSBxmmxmm/m128sse2Subtract Packed Signed Integers with Signed Saturation
0FE9rPSUBSWmmmm/m64mmxSubtract Packed Signed Integers with Signed Saturation
660FE9rPSUBSWxmmxmm/m128sse2Subtract Packed Signed Integers with Signed Saturation
0FEArPMINSWmmmm/m64sse1Minimum of Packed Signed Word Integers
660FEArPMINSWxmmxmm/m128sse1Minimum of Packed Signed Word Integers
0FEBrPORmmmm/m64mmxBitwise Logical OR
660FEBrPORxmmxmm/m128sse2Bitwise Logical OR
0FECrPADDSBmmmm/m64mmxAdd Packed Signed Integers with Signed Saturation
660FECrPADDSBxmmxmm/m128sse2Add Packed Signed Integers with Signed Saturation
0FEDrPADDSWmmmm/m64mmxAdd Packed Signed Integers with Signed Saturation
660FEDrPADDSWxmmxmm/m128sse2Add Packed Signed Integers with Signed Saturation
0FEErPMAXSWmmmm/m64sse1Maximum of Packed Signed Word Integers
660FEErPMAXSWxmmxmm/m128sse1Maximum of Packed Signed Word Integers
0FEFrPXORmmmm/m64mmxLogical Exclusive OR
660FEFrPXORxmmxmm/m128sse2Logical Exclusive OR
F20FF0rLDDQUxmmm128sse3Load Unaligned Integer 128 Bits
0FF1rPSLLWmmmm/m64mmxShift Packed Data Left Logical
660FF1rPSLLWxmmxmm/m128sse2Shift Packed Data Left Logical
0FF2rPSLLDmmmm/m64mmxShift Packed Data Left Logical
660FF2rPSLLDxmmxmm/m128sse2Shift Packed Data Left Logical
0FF3rPSLLQmmmm/m64mmxShift Packed Data Left Logical
660FF3rPSLLQxmmxmm/m128sse2Shift Packed Data Left Logical
0FF4rPMULUDQmmmm/m64sse2Multiply Packed Unsigned DW Integers
660FF4rPMULUDQxmmxmm/m128sse2Multiply Packed Unsigned DW Integers
0FF5rPMADDWDmmmm/m64mmxMultiply and Add Packed Integers
660FF5rPMADDWDxmmxmm/m128sse2Multiply and Add Packed Integers
0FF6rPSADBWmmmm/m64sse1Compute Sum of Absolute Differences
660FF6rPSADBWxmmxmm/m128sse1Compute Sum of Absolute Differences
0FF7rD31MASKMOVQm64mmmmsse1Store Selected Bytes of Quadword
660FF7rMASKMOVDQUm128xmmxmmsse2Store Selected Bytes of Double Quadword
0FF8rPSUBBmmmm/m64mmxSubtract Packed Integers
660FF8rPSUBBxmmxmm/m128sse2Subtract Packed Integers
0FF9rPSUBWmmmm/m64mmxSubtract Packed Integers
660FF9rPSUBWxmmxmm/m128sse2Subtract Packed Integers
0FFArPSUBDmmmm/m64mmxSubtract Packed Integers
660FFArPSUBDxmmxmm/m128sse2Subtract Packed Integers
0FFBrPSUBQmmmm/m64sse2Subtract Packed Quadword Integers
660FFBrPSUBQxmmxmm/m128sse2Subtract Packed Quadword Integers
0FFCrPADDBmmmm/m64mmxAdd Packed Integers
660FFCrPADDBxmmxmm/m128sse2Add Packed Integers
0FFDrPADDWmmmm/m64mmxAdd Packed Integers
660FFDrPADDWxmmxmm/m128sse2Add Packed Integers
0FFErPADDDmmmm/m64mmxAdd Packed Integers
660FFErPADDDxmmxmm/m128sse2Add Packed Integers

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General notes:

  1. 90 NOP
    1. 90 NOP is not really aliased to XCHG eAX, eAX instruction. This is important in 64-bit mode where the implicit zero-extension to RAX does not happen
  2. LAHF, SAHF
    1. Invalid on early steppings of EM64T architecture; that's why they need CPUID.80000001H:ECX.LAHF-SAHF[bit 0]
  3. SAL
    1. sandpile.org -- IA-32 architecture -- opcode groups
  4. D6 and F1 opcodes
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 3: System Programming Guide, Interrupt and Exception Handling
  5. FSTP1
    1. Christian Ludloff wrote: While FSTP (D9 /3, mod < 11b), FSTP8 (DF /2, mod = 11b), and FSTP9 (DF /3, mod = 11b) do signal stack underflow, FSTP1 (D9 /3, mod = 11b) does not.
  6. FNENI and FNDISI
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Processor Control Instructions: The 8087 instructions FENI and FDISI perform no function in the 80287. If these opcodes are detected in an 80286/80287 instruction stream, the 80287 will perform no specific operation and no internal states will be affected.
  7. FNSETPM
    1. INTEL 80387 PROGRAMMER'S REFERENCE MANUAL 1987, 6.1.2 Independent of CPU Addressing Modes: Unlike the 80287, the 80387 is not sensitive to the addressing and memory management of the CPU. The 80387 operates the same regardless of whether the 80386 CPU is operating in real-address mode, in protected mode, or in virtual 8086 mode.
  8. FFREEP
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FFREE ST(i) and pop stack
    2. Intel Architecture Optimization Reference Manual PIII, Table C-1 Pentium II and Pentium III Processors Instruction to Decoder Specification
    3. AMD Athlon Processor x86 Code Optimization Guide, Chapter 9, Use FFREEP Macro to Pop One Register from the FPU Stack
    4. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  9. X87 aliases
    1. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  10. INT1, ICEBP
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    3. Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
  11. REP prefixes
    1. Flags aren't updated until after the last iteration to make the operation faster
  12. TEST
    1. sandpile.org -- IA-32 architecture -- opcode groups
    2. Christian Ludloff wrote: While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it.
    3. AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte and Two-Byte Opcode ModRM Extensions
  13. CALLF, JMPF
    1. AMD64 Architecture Programmer's Manual Volume 3: If the operand-size is 32 or 64 bits, the operand is a 16-bit selector followed by a 32-bit offset. (On AMD64 architecture, 64-bit offset is not supported)
  14. SMSW r32/64
    1. Some processors support reading whole CR0 register, causing a security flaw.
  15. SYSCALL
    1. On AMD64 architecture, SYSCALL is valid also in legacy mode
  16. 0F0D NOP
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. AMD architecture maps 3DNow! PREFETCH instructions here
  17. Hintable NOP
    1. See U.S. Patent 5,701,442
    2. sandpile.org -- IA-32 architecture -- opcode groups
  18. MOV from/to CRn, DRn, TRn
    1. Christian Ludloff wrote: For the MOVs from/to CRx/DRx/TRx, mod=00b/01b/10b is aliased to 11b.
    2. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: This instruction is always treated as a register-to-register instruction, regardless of the encoding of the MOD field in the MODR/M byte.
  19. SYSENTER
    1. On AMD64 architecture, SYSENTER is valid only in legacy mode.
  20. SYSEXIT
    1. On AMD64 architecture, SYSEXIT is not valid in long mode.
  21. GETSEC Leaf Functions
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z: The GETSEC instruction supports multiple leaf functions. Leaf functions are selected by the value in EAX at the time GETSEC is executed. The following leaf functions are available: CAPABILITIES, ENTERACCS, EXITAC, SENTER, SEXIT, PARAMETERS, SMCTRL, WAKEUP. GETSEC instruction operands are specific to selected leaf function.
  22. MOVQ
    1. On AMD64 architecture, only MOVD mnemonic is used.
  23. CMOVcc
    1. The destination register operand is zero-extended to 64 bits even if the condition is not satisfied.
  24. SETcc
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The reg field in the ModR/M byte is unused.
  25. CMPXCHG with memory operand
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction can be used with a LOCK prefix …. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison.
    2. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: CMPXCHG always does a read-modify-write on the memory operand.
  26. LFS, LGS, LSS
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: Executing LFS, LGS, or LSS with a 64-bit operand size only loads a 32-bit general purpose register and the specified segment register. (On AMD64 architecture, 64-bit offset is not supported)
  27. 0FB9 UD
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. sandpile.org -- IA-32 architecture -- two byte opcodes
  28. BSF, BSR
    1. On AMD64 architecture, BSF and BSR instructions act differently if the content of the source operand is 0
  29. CMPXCHG8B, CMPXCHG16B
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction can be used with a LOCK prefix …. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison.
    2. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The CMPXCHG8B and CMPXCHG16B instructions always do a read-modify-write on the memory operand.
    3. CMPXCHG16B is invalid on early steppings of AMD64 architecture.
  30. BSWAP r16
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: When the BSWAP instruction references a 16-bit register, the result is undefined.
    2. AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions: The result of applying the BSWAP instruction to a 16-bit register is undefined.
  31. MASKMOVQ
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction causes a transition from x87 FPU to MMX technology state.
  32. Short and near jumps
    1. Use of operand-size prefix in 64-bit mode may result in implementation-dependent behaviour; on AMD64 architecture, this prefix acts as expected
  33. Intel VMX
    1. Intel VMX is not binary-compatible with AMD SVM
  34. Intel SSE4
    1. AMD64 architecture does not support SSE4 instructions but PTEST as part of SSE5

Notes for the Ring Level, used in case of f mark:

  1. rFlags.IOPL
  2. CR4.TSD[bit 2]
  3. CR4.PCE[bit 8]

Create a hypertext reference to this edition's opcode (append hexadecimal opcode at the end of the following line):

http://ref.x86asm.net/coder64.html#x

32/64-bit ModR/M Byte

REX.R=1
r8(/r) without REX prefixALCLDLBLAHCHDHBH
r8(/r) with any REX prefixALCLDLBLSPLBPLSILDILR8BR9BR10BR11BR12BR13BR14BR15B
r16(/r)AXCXDXBXSPBPSIDIR8WR9WR10WR11WR12WR13WR14WR15W
r32(/r)EAXECXEDXEBXESPEBPESIEDIR8DR9DR10DR11DR12DR13DR14DR15D
r64(/r)RAXRCXRDXRBXRSPRBPRSIRDIR8R9R10R11R12R13R14R15
mm(/r)MM0MM1MM2MM3MM4MM5MM6MM7MM0MM1MM2MM3MM4MM5MM6MM7
xmm(/r)XMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7XMM8XMM9XMM10XMM11XMM12XMM13XMM14XMM15
sregESCSSSDSFSGSres.res.ESCSSSDSFSGSres.res.
eeeCR0invdCR2CR3CR4invdinvdinvdCR8invdinvdinvdinvdinvdinvdinvd
eeeDR0DR1DR2DR3DR41DR51DR6DR7invdinvdinvdinvdinvdinvdinvdinvd
(In decimal) /digit (Opcode)0123456701234567
(In binary) REG =000001010011100101110111000001010011100101110111
Effective AddressEffective Address REX.B=1ModR/MValue of ModR/M Byte (in Hex)Value of ModR/M Byte (in Hex)
[RAX/EAX][R8/R8D]0000000081018202830380008101820283038
[RCX/ECX][R9/R9D]00101091119212931390109111921293139
[RDX/EDX][R10/R10D]010020A121A222A323A020A121A222A323A
[RBX/EBX][R11/R11D]011030B131B232B333B030B131B232B333B
[sib][sib]100040C141C242C343C040C141C242C343C
[RIP/EIP]+disp32[RIP/EIP]+disp32101050D151D252D353D050D151D252D353D
[RSI/ESI][R14/R14D]110060E161E262E363E060E161E262E363E
[RDI/EDI][R15/R15D]111070F171F272F373F0F07171F272F373F
[RAX/EAX]+disp8[R8/R8D]+disp80100040485058606870784048505860687078
[RCX/EDX]+disp8[R9/R9D]+disp800141495159616971794149515961697179
[RDX/EDX]+disp8[R10/R10D]+disp8010424A525A626A727A424A525A626A727A
[RBX/EBX]+disp8[R11/R11D]+disp8011434B535B636B737B434B535B636B737B
[sib]+disp8[sib]+disp8100444C545C646C747C444C545C646C747C
[RBP/EBP]+disp8[R13/R13D]+disp8101454D555D656D757D454D555D656D757D
[RSI/ESI]+disp8[R14/R14D]+disp8110464E565E666E767E464E565E666E767E
[RDI/EDI]+disp8[R15/R15D]+disp8111474F575F676F777F474F575F676F777F
[RAX/EAX]+disp32[R8/R8D]+disp321000080889098A0A8B0B880889098A0A8B0B8
[RCX/ECX]+disp32[R9/R9D]+disp3200181899199A1A9B1B981899199A1A9B1B9
[RDX/EDX]+disp32[R10/R10D]+disp32010828A929AA2AAB2BA828A929AA2AAB2BA
[RBX/EBX]+disp32[R11/R11D]+disp32011838B939BA3ABB3BB838B939BA3ABB3BB
[sib]+disp32[sib]+disp32100848C949CA4ACB4BC848C949CA4ACB4BC
[RBP/EBP]+disp32[R13/R13D]+disp32101858D959DA5ADB5BD858D959DA5ADB5BD
[RSI/ESI]+disp32[R14/R14D]+disp32110868E969EA6AEB6BE868E969EA6AEB6BE
[RDI/EDI]+disp32[R15/R15D]+disp32111878F979FA7AFB7BF878F979FA7AFB7BF
AL/AX/EAX/RAX/ST0/MM0/XMM0R8B/R8W/R8D/R8/ST0/MM0/XMM811000C0C8D0D8E0E8F0F8C0C8D0D8E0E8F0F8
CL/CX/ECX/RCX/ST1/MM1/XMM1R9B/R9W/R9D/R9/ST1/MM1/XMM9001C1C9D1D9E1E9F1F9C1C9D1D9E1E9F1F9
DL/DX/EDX/RDX/ST2/MM2/XMM2R10B/R10W/R10D/R10/ST2/MM2/XMM10010C2CAD2DAE2EAF2FAC2CAD2DAE2EAF2FA
BL/BX/EBX/RBX/ST3/MM3/XMM3R11B/R11W/R11D/R11/ST3/MM3/XMM11011C3CBD3DBE3EBF3FBC3CBD3DBE3EBF3FB
AH/SP/ESP/RSP/ST4/MM4/XMM4R12B/R12W/R12D/R12/ST4/MM4/XMM12100C4CCD4DCE4ECF4FCC4CCD4DCE4ECF4FC
CH/BP/EBP/RBP/ST5/MM5/XMM5R13B/R13W/R13D/R13/ST5/MM5/XMM13101C5CDD5DDE5EDF5FDC5CDD5DDE5EDF5FD
DH/SI/ESI/RSI/ST6/MM6/XMM6R14B/R14W/R14D/R14/ST6/MM6/XMM14110C6CED6DEE6EEF6FEC6CED6DEE6EEF6FE
BH/DI/EDI/RDI/ST7/MM7/XMM7R15B/R15W/R15D/R15/ST7/MM7/XMM15111C7CFD7DFE7EFF7FFC7CFD7DFE7EFF7FF

32/64-bit SIB Byte

REX.B=1
r64RAXRCXRDXRBXRSP1RSIRDIR8R9R10R11R122R14R15
r32EAXECXEDXEBXESP1ESIEDIR8DR9DR10DR11DR12D2R14DR15D
(In decimal) Base =0123456701234567
(In binary) Base =000001010011100101110111000001010011100101110111
Scaled IndexScaled Index
REX.X=1
SSIndexValue of SIB Byte (in Hex)Value of SIB Byte (in Hex)
[RAX/EAX][R8/R8D]0000000010203040506070001020304050607
[RCX/ECX][R9/R9D]00108090A0B0C0D0E0F08090A0B0C0D0E0F
[RDX/EDX][R10/R10D]01010111213141516171011121314151617
[RBX/EBX][R11/R11D]01118191A1B1C1D1E1F18191A1B1C1D1E1F
none[R12/R12D]10020212223242526272021222324252627
[RBP/EBP][R13/R13D]10128292A2B2C2D2E2F28292A2B2C2D2E2F
[RSI/ESI][R14/R14D]11030313233343536373031323334353637
[RDI/EDI][R15/R15D]11138393A3B3C3D3E3F38393A3B3C3D3E3F
[RAX/EAX*2][R8/R8D*2]0100040414243444546474041424344454647
[RCX/ECX*2][R9/R9D*2]00148494A4B4C4D4E4F48494A4B4C4D4E4F
[RDX/EDX*2][R10/R10D*2]01050515253545556575051525354555657
[RBX/EBX*2][R11/R11D*2]01158595A5B5C5D5E5F58595A5B5C5D5E5F
none[R12/R12D*2]10060616263646566676061626364656667
[RBP/EBP*2][R13/R13*2]10168696A6B6C6D6E6F68696A6B6C6D6E6F
[RSI/ESI*2][R14/R14D*2]11070717273747576777071727374757677
[RDI/EDI*2][R15/R15D*2]11178797A7B7C7D7E7F78797A7B7C7D7E7F
[RAX/EAX*4][R8/R8D*4]1000080818283848586878081828384858687
[RCX/ECX*4][R9/R9D*4]00188898A8B8C8D8E8F88898A8B8C8D8E8F
[RDX/EDX*4][R10/R10D*4]01090919293949596979091929394959697
[RBX/EBX*4][R11/E11D*4]01198999A9B9C9D9E9F98999A9B9C9D9E9F
none[R12/R12D*4]100A0A1A2A3A4A5A6A7A0A1A2A3A4A5A6A7
[RBP/EBP*4][R13/R13D*4]101A8A9AAABACADAEAFA8A9AAABACADAEAF
[RSI/ESI*4][R14/R14D*4]110B0B1B2B3B4B5B6B7B0B1B2B3B4B5B6B7
[RDI/EDI*4][R15/R15D*4]111B8B9BABBBCBDBEBFB8B9BABBBCBDBEBF
[RAX/EAX*8][R8/R8D*8]11000C0C1C2C3C4C5C6C7C0C1C2C3C4C5C6C7
[RCX/ECX*8][R9/R9D*8]001C8C9CACBCCCDCECFC8C9CACBCCCDCECF
[RDX/EDX*8][R10/R10D*8]010D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7
[RBX/EBX*8][R11/R11D*8]011D8D9DADBDCDDDEDFD8D9DADBDCDDDEDF
none[R12/R12D*8]100E0E1E2E3E4E5E6E7E0E1E2E3E4E5E6E7
[RBP/EBP*8][R13/R13D*8]101E8E9EAEBECEDEEEFE8E9EAEBECEDEEEF
[RSI/ESI*8][R14/R14D*8]110F0F1F2F3F4F5F6F7F0F1F2F3F4F5F6F7
[RDI/EDI*8][R15/R15D*8]111F8F9FAFBFCFDFEFFF8F9FAFBFCFDFEFF
SIB Note 1
Mod bitsbase
00disp32
01RBP/EBP+disp8
10RBP/EBP+disp32
 
SIB Note 2
Mod bitsbase
00disp32
01R13/R13D+disp8
10R13/R13D+disp32

16-bit ModR/M Byte

r8(/r)ALCLDLBLAHCHDHBH
r16(/r)AXCXDXBXSPBPSIDI
r32(/r)EAXECXEDXEBXESPEBPESIEDI
mm(/r)MM0MM1MM2MM3MM4MM5MM6MM7
xmm(/r)XMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7
sregESCSSSDSFSGSres.res.
eeeCR0invdCR2CR3CR4invdinvdinvd
eeeDR0DR1DR2DR3DR41DR51DR6DR7
(In decimal) /digit (Opcode)01234567
(In binary) REG =000001010011100101110111
Effective AddressModR/MValue of ModR/M Byte (in Hex)
[BX+SI]000000008101820283038
[BX+DI]0010109111921293139
[BP+SI]010020A121A222A323A
[BP+DI]011030B131B232B333B
[SI]100040C141C242C343C
[DI]101050D151D252D353D
disp16110060E161E262E363E
[BX]111070F171F272F373F
[BX+SI]+disp8010004048505860687078
[BX+DI]+disp80014149515961697179
[BP+SI]+disp8010424A525A626A727A
[BP+DI]+disp8011434B535B636B737B
[SI]+disp8100444C545C646C747C
[DI]+disp8101454D555D656D757D
[BP]+disp8110464E565E666E767E
[BX]+disp8111474F575F676F777F
[BX+SI]+disp161000080889098A0A8B0B8
[BX+DI]+disp1600181899199A1A9B1B9
[BP+SI]+disp16010828A929AA2AAB2BA
[BP+DI]+disp16011838B939BA3ABB3BB
[SI]+disp16100848C949CA4ACB4BC
[DI]+disp16101858D959DA5ADB5BD
[BP]+disp16110868E969EA6AEB6BE
[BX]+disp16111878F979FA7AFB7BF
AL/AX/EAX/ST0/MM0/XMM011000C0C8D0D8E0E8F0F8
CL/CX/ECX/ST1/MM1/XMM1001C1C9D1D9E1E9F1F9
DL/DX/EDX/ST2/MM2/XMM2010C2CAD2DAE2EAF2FA
BL/BX/EBX/ST3/MM3/XMM3011C3CBD3DBE3EBF3FB
AH/SP/ESP/ST4/MM4/XMM4100C4CCD4DCE4ECF4FC
CH/BP/EBP/ST5/MM5/XMM5101C5CDD5DDE5EDF5FD
DH/SI/ESI/ST6/MM6/XMM6110C6CED6DEE6EEF6FE
BH/DI/EDI/ST7/MM7/XMM7111C7CFD7DFE7EFF7FF
ModR/M Note 1: Debug Registers DR4 and DR5
References to debug registers DR4 and DR5 cause an undefined opcode (#UD) exception to be generated when CR4.DE[bit 3] (Debugging Extensions) set; when clear, processor aliases references to registers DR4 and DR5 to DR6 and DR7 for compatibility with software written to run on earlier IA-32 processors.
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