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  • Paper Accepted in IEEE Transactions Circuits and Systems (2019) FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings
  • Paper Accepted in ACM Transactions on TRETS (2018) Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve 
  • Paper Accepted in VLSID'17Compact Implementations of FPGA-Based PUFs with Enhanced Performance
  • Paper Accepted in SECITC'15SCA Resistance Analysis on FPGA Implementations of Sponge based MAC-PHOTON
  • Paper Accepted in INDOCRYPT’14: A Very Compact FPGA Implementation of LED and PHOTON
  • Co-organizing Chair of ASK 2014, December, 19-22, Chennai, India.

Welcome 

  I am a Scientist at Society for Electronic Transactions and Security (SETS), Chennai, India. I also worked as a Research Associate at SPMS, Nanyang Technological University (NTU), Singapore. 

   In Jan 2016, I started my Ph.D. program in Computer Science Engineering at Indraprastha Institute of Information Technology (IIIT-Delhi) under the supervision of Dr. Somitra Kumar Sanadhya and Dr. Mohammad Hashmi

Research Interests: Hardware Security and Trust, with emphasis on: 

        1. Physically Unclonable Functions (PUFs) and TRNG

        2Efficient and Secure Hardware Implementations of Cryptographic Primitives.

        3. Side-Channel Attacks (SCA) and Hardware Trojan Detection 

Served as a Reviewer for

  • Journals/Transactions
    • IEEE Trans on Inf. Forensics and Security (TIFS), 
    • IEEE Trans on Circuits and Systems (TCAS-I), 
    • ACM Transactions on Reconfigurable Technology and Systems (TRETS), 
    • IETE Journal of Education and Journal of Egyptian Informatics. 
  • Conferences: ACNS2017 (Subreviewer), ICISC 2016, Inscrypt 2016 (Subreviewer)

Contact Me

Address: Society for Electronic Transactions and Security [SETS]

M.G.R Knowledge City, CIT Campus,

Taramani, Chennai, India - 600113

E-mail:nallananth[at]gmail.com

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