Nima Aghaee

Embedded Systems at Guideline Geo


Contact Information


Personal: nima_ag[at]yahoo.com 
              (+46) 76-0812771

                       
Office:     nima.aghaee[at]guidelinegeo.com 
              (+46) 72-2484636
 

Education

PhD in Computer Systems, CUGSLinköping University
MAS in Embedded Systems Design, ALaRI Institure, Switzerland
MSc in Electronics EngineeringTarbiat Modares University, Tehran
BS in Electronics EngineeringShahid Beheshti University, Tehran

Experience

2016 Embedded Systems Engineer, R&D, Guideline Geo AB
2011 PhD Student, ESLAB, Linkoping University
2010 Research Assistant, ESLAB, Linkoping University
2008 Embedded Designer, Rasa
2008 Teacher, Azad University

Publications 

PhD thesis is available here (link).

Journals
  • Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs,  TVLSI 2015. IEEE Transactions on Very Large Scale Integration Systems. (link)
  • A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs, Jetta 2015. Journal of Electronic Testing: Theory and Applications. (link)
  • Process-variation and Temperature Aware SoC Test Scheduling Technique, Jetta 2013. Journal of Electronic Testing: Theory and Applications. (link)
Conferences
  • Efficient Test Application for Rapid Multi-Temperature Testing, GLSVLSI 2015. 25th ACM's Great Lakes VLSI Symposium. (link)
  • An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICsASP-DAC 2015. Asia and South Pacific Design Automation Conference. (link)
  • An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs, DATE 2014. Design, Automation and Test in Europe. (link)
  • Process-Variation Aware Multi-Temperature Test Scheduling, VLSID 2014. 27th International Conference on VLSI Design. (link)
  • Temperature-Gradient Based Test Scheduling for 3D Stacked ICs, ICECS 2013. 20th IEEE International Conference on Electronics, Circuits, and Systems. (link)
  • Temperature-Gradient Based Burn-In for 3D Stacked ICsSSoCC 2013. 12th Swedish System-on-Chip Conference, May. 2013. (not reviewed, not printed, link)
  • Process-Variation and Temperature Aware SoC Test Scheduling Using Particle Swarm Optimization, IDT 2011. 6th IEEE International Design and Test Workshop, Dec. 2011. (link)
  • Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation, DSD 2011. 14th Euromicro Conference on Digital System Design, Aug. 2011. (link)
  • Heuristics for Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation, SSoCC 2011. 11th Swedish System-on-Chip Conference, May. 2011. (not reviewed, not printed, link)
  • Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation, ATS 2010. IEEE 19th Asian Test Symposium, Dec. 2010. (link)
  • Design of a Pipelined R4SDF Processor, EUSIPCO 2009. 17th European Signal Processing Conference, Aug. 2009. (link)
  • A Pipelined Architecture for a 20-point PFA, TENCON 2006. 2006 IEEE Region 10 Conference, Nov. 2006. (link)

Misc

Contributed to HotSpot 5.01.