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The MV5 Simulator 

An Event-driven, Cycle-accurate Simulator for Heterogeneous Manycore Architectures

MV5 is a reconfigurable simulator for heterogeneous multicore/manycore architectures. It is based on M5v2.0 beta 4.

Typical usage: 
  • Simulating data-parallel applications on SIMT cores that operate over directory-based cache hierarchies. 
  • You can also add out-of-order cores to have a heterogeneous system, and all different types of cores can operate under the same address space through the same cache hierarchy.
Features
  • Single-Instruction, Multiple-Threads (SIMT) cores
  • Directory-based Coherence Cache: MESI/MSI. (Not based on gem)
  • Interconnect: Fully connected and 2D Mesh. (Not based on gem)
  • Threading API/Library in system emulation mode (Not support for full-system simulation)

OwnerDescriptionDue DateComplete
Jiayuan add cache latency stats   
Jiayuan fix compile warning (see mail Feb 11, 2011 by Adwait)   
Showing 2 items from page To-Dos sorted by Due Date, Owner, Complete. View more »

The MV5 Simulator is developed at the LAVA group in the Department of Computer Science, UVA. We also appreciate the support from the M5 team as well as external contributers

This simulator was developed in part with support from the NSF under grant no. IIS-0612049, funding from the Semiconductor Research Corporation under task 1607, grants from Intel Research and NVIDIA Research, and an NVIDIA Ph.D. fellowship.

Research projects based on MV5 have been published in ISCA'10, ICCD'09, and IPDPS'10.

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License

Current release: MV5 version 0.8, release date June 1, 2010.




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