MV5 is a reconfigurable simulator for heterogeneous multicore/manycore architectures. It is based on M5v2.0 beta 4.
The MV5 Simulator is developed at the LAVA group in the Department of Computer Science, UVA. We also appreciate the support from the M5 team as well as external contributers.
This simulator was developed in part with support from the NSF under grant no. IIS-0612049, funding from the Semiconductor Research Corporation under task 1607, grants from Intel Research and NVIDIA Research, and an NVIDIA Ph.D. fellowship.
Research projects based on MV5 have been published in ISCA'10, ICCD'09, and IPDPS'10.
Current release: MV5 version 0.8, release date June 1, 2010.