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MSP430G2xxx

If you have ever been confused by the array of different G2/Value Line chips, then this page will take away the mystery.  TI uses a fairly logical numbering scheme and with just a little bit of study much is revealed.  All chips in the G2 series have the following naming format:

MSP430G2xyz

The x digit represents the amount of Flash memory in kilobytes:

0 =  0.5
1 =  1
2 =  2
3 =  4
4 =  8
5 = 16 

The yz digits combined represent the chip's peripheral options.  Furthermore, the z digit represents the chip's generation.  Within each generation, a complete or nearly-complete matrix of chip options is available.  As you can see, there are only a limited number of peripheral combinations.

All chips in the first generation are 14 pin DIP.  All chips in the second and third generations are 20 pin DIP and support cap-touch.

2xx1 - First Generation (0.5, 1, 2 KB Flash - complete matrix for 1, 2 KB Flash)

01 = 1 timer, 128 RAM (this is the only configuration available with 0.5 KB Flash)
21 = 1 timer, 128 RAM, USI
11 = 1 timer, 128 RAM, Comp A+
31 = 1 timer, 128 RAM, USI, Temp, ADC

2xx2 - Second Generation (1, 2, 4, 8 KB Flash - complete matrix available)

02 = 1 timer, 256 RAM, USI
12 = 1 timer, 256 RAM, Comp A+
32 = 1 timer, 256 RAM, USI, Temp, ADC10
52 = 1 timer, 256 RAM, USI, Comp A+, Temp, ADC10

2xx3 - Third Generation (1, 2, 4, 8, 16 KB Flash - nearly complete matrix available)

03 = 2 timer, 256/512 RAM, UART (1KB Flash n/a)
13 = 2 timer, 256/512 RAM, UART, Comp A+ (1KB Flash n/a)
33 = 2 timer, 256/512 RAM, UART, Temp, ADC10
53 = 2 timer, 256/512 RAM, UART, Comp A+, Temp, ADC10

Chips with 1 - 4 KB of Flash are equipped with 256 bytes of RAM.
Chips with 8 - 16 KB of Flash are equipped with 512 bytes of RAM.

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