Mingxing Tan

Email: tanmx.star@gmail.com

I have joined Google Inc. (Mountain View, CA).

Publications

  • [TCAD'17] Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests [pdf]
    Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, and Zhiru Zhang.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.
  • [ICCAD'15] ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests [pdf]
    Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, and Zhiru Zhang.
    Proceedings of the 34th International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov 2-6, 2015.
  • [ICPP'15] An Energy-Efficient Branch Prediction with Grouped Global History [pdf]
    Mingkai Huang, Dan He, XIanhua Liu, Mingxing Tan, and Xu Cheng.
    Proceedings of the 44th International Conference on Parallel Processing (ICPP), Beijing, Chain, Sep 1-4, 2015.
  • [DAC'15] Area-Efficient Pipelining for FPGA-Targeted High-Level Synthesis [link, pdf]
    Ritchie Zhao, Mingxing Tan, Steve Dai, and Zhiru Zhang.
    Proceedings of the 52nd Design Automation Conference (DAC), San Francisco, US, June 7-11, 2015.
  • [FPGA'15] Mapping-Aware Constrained Scheduling for LUT-Based FPGAs [link, pdf]
    Mingxing Tan, Steve Dai, Udit Gupta, and Zhiru Zhang.
    Proceedings of the 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 22-24, 2015.
  • [MICRO'14] Architectural Specialization for Inter-Iteration Loop Dependence Patterns [link, pdf]
    Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, and Christopher Batten.
    Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, UK, December 13-17, 2014.
  • [ICCAD'14] Multithreaded Pipeline Synthesis for Data-Parallel Kernels [link, pdf]
    Mingxing Tan, Bin Liu, Steve Dai and Zhiru Zhang.
    Proceedings of the 33rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, November 3-6, 2014.
  • [HCP'14] XLOOPS: Explicit Loop Specialization [pdf]
    Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, and Christopher Batten.
    International Workshop on Heterogeneous Computing Platforms (HCP) held in conjunction with ICCAD-33 (HCP), San Jose, USA, November 3-6, 2014.
  • [ISLPED'14] CASA: Correlation-Aware Speculative Adders [link, pdf]
    Gai Liu, Ye Tao, Mingxing Tan and Zhiru Zhang.
    Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, USA, August 11-13, 2014.
  • [DAC'14] Flushing-Enabled Loop Pipelining for High-Level Synthesis [link, pdf]
    Steve Dai, Mingxing Tan, Kecheng Hao and Zhiru Zhang.
    Proceedings of the 51st Design Automation Conference (DAC), San Francisco, US, June 7-11, 2014.
  • [DAC'14 Poster] CASA: Correlation-Aware Speculative Adders
    Gai Liu, Ye Tao, Mingxing Tan and Zhiru Zhang.
    Design Automation Conference (DAC) (Work-in-Progress Poster) , San Francisco, US, June 7-11, 2014.
  • [JCRD'13] An Indirect Branch Prediction for Interpreters [pdf]
    Mingkai Huang, Xianhua Liu, Mingxing Tan, Zichao Xie, Xu Cheng.
    Journal of Computer Research and Development (JCRD, in Chinese), accepted in 2013.
  • [ICS'12] CVP: An Energy-Efficient Indirect Branch Prediction with Compiler-Guided Value Pattern [link, pdf]
    Mingxing Tan, Xianhua Liu, Dong Tong, Xu Cheng.
    Proceedings of the 26th ACM/SIGARCH International Conference on Supercomputing (ICS), pages 111-120, Venice, Italy, June 25-29, 2012.
  • [DATE'12] Energy-Efficient Branch Prediction with Compiler-Guided History Stack [link, pdf]
    Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng.
    Proceedings of the 15th Design, Automation and Test in Europe (DATE), pages 449-454, Dresden, Germany, March 12-16, 2012.
  • [CJE'12] Compiler-Assisted Value Correlation for Indirect Branch Prediction
    Mingxing Tan, Xianhua Liu, Jiyu Zhang, Dong Tong, Xu Cheng.
    Chinese Journal of Electronics , Vol.21(3), pages 414-418, 2012.
  • [AES'12] A Hybrid Value Correlation Based Indirect Jump Prediction
    Mingxing Tan, Xianhua Liu, Jiyu Zhang, Dong Tong, Xu Cheng.
    Acta Electronica Sinica(in chinese), Vol. 40(11), pages 2298-2302, 2012.
  • [AES'12] Non-Overlapped Modulo Scheduling with Optimized Backtracking Model [pdf]
    Mingxing Tan, Xianhua Liu, Jiyu Zhang, Xu Cheng.
    Acta Electronica Sinica (in chinese), Vol. 40(8), pages 1681-1686, 2012.
  • [AES'12] Automatic Instruction-Set Extension for Bitwise-Operation-Intensive Applications [pdf]
    Jiyu Zhang, Xianhua Liu, Mingxing Tan, Xu Cheng, Jason Cong.
    Acta Electronica Sinica (in chinese), Vol. 40(2), pages 209-214, 2012.
  • [FPGA'10] Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration [link, pdf]
    Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, and Jason Cong.
    Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, California, February 21-23, 2010.
  • [IWLS'09] Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions [pdf]
    Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, and Jason Cong.
    Proceedings of the 18th International Workshop on Logic & Synthesis (IWLS), Berkeley, California, July 31 - August 2, 2009.
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