Mike Hutton Patents

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I update this every once in a while.  For a current list of issued patents go to US Patent & Trademark Office.   

Issued Patents

8,640,067 M. Hutton and D. Lewis, Method and apparatus for implementing a field programmable gate array skew, Jan 28, 2014. 

8,601,424 M. Hutton, G. Baeckler, J. Yuan, C. Wysocki and P. Djahani, Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers, Dec 3, 2013.

8,593,174 J. Schleicher, R. Yuan, B. Pedersen, S. Kaptanoglu, G. Baeckler, D. Lewis, M. Hutton, A. Lee, R. Saini, and H. Kim.  Omnibus logic element for packing or fracturing.  Nov 26, 2012.

8,542,032 M. Hutton and I.Rahim, Integrated circuits with interconnect selection circuitry, Sept 24, 2013.

8,521,801 J. Pistorius and M. Hutton, Configurable hybrid adder circuitry, Aug 27, 2013.

8,519,740 M. Hutton and D. Lewis, Integrated circuits with shared interconnect busses, Aug 27, 2013.

8,402,408 B. van Antwerpen, M. Hutton, G. Baeckler and R. Yuan, Register retiming technique, March 19, 2013.

8,381,142 M. Hutton.  Using a Timing Exception to Postpone Retiming.  Feb19, 2013.

8,314,636 M. Hutton, J. Schleicher and D. Mansur.  Field-programmable gate array with integrated application specific integrated circuit fabric.  Nov 20, 2012.

8,237,465 J. Schleicher, R. Yuan, B. Pedersen, S. Kaptanoglu, G. Baeckler, D. Lewis, M. Hutton, A. Lee, R. Saini, and H. Kim.  Omnibus logic element for packing or fracturing.  Aug 7, 2012.

8,185,854 M. Hutton and J. Govig, Method and apparatus for performing parallel slack computation within a shared netlist region, May 22, 2012.

8,166,427 S. Pathak, B. van Antwerpen, M. Hutton and A. Leaver, Tracing and reporting registers removed during synthesis, April 24, 2012.

8,112,728 M. Hutton and D. Karchmer, Early timing estimation of timing statistical properties of placement,  February 7, 2012.

8,108,812 B. van Antwerpen, M. Hutton, G. Baeckler and R. Yuan, Register retiming technique, January 31, 2012

8,082,526 M. Hutton and S. Kaptanoglu.   Dedicated crossbar and barrel shifter block on programmable logic resources .  December 20, 2011.

8,072,238 M. Hutton.  Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order functions.  December 6, 2011.

8,020,027 M. Hutton.  Timing control in a specialized processing block.  September 13, 2011.

8,001,499 G. Baeckler, D. Mendel and M. Hutton.  Circuit-type pragma for computer aided design tools.  August 16, 2011.

7,911,230 J. Schleicher, R. Yuan, B. Pedersen, S. Kaptanoglu, G. Baeckler, D. Lewis, M. Hutton, A. Lee, R. Saini, and H. Kim.  Omnibus logic element for packing or fracturing.  March 22, 2011.

7,902,864 M. Hutton, K. Duwel and G. Baeckler.  Heterogeneous labs.  March 8, 2011.

7,890,910 M. Hutton, G. Baeckler, J. Yuan, C. Wysocki and P. Djahani.  Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers.  February 15, 2011.

7,839,167 T. Ngai, B. Pedersen, S. Shumarayev, J. Schleicher, W-J Huang, M. Hutton, V. Maruri, R. Patel, P. Kazarian, A. Leaver, D. Mendel and J. Park,  Interconnection and input/output resources for programmable logic integrated circuit devices.  Jan 20, 2009. 

7,839,165 M. Hutton and A. Lee.  User-accessible freeze logic for dynamic power reduction and associated methods.  November 23, 2010.

7,827,433 M. Hutton.  Time-multiplexed routing for reducing pipelining registers.  November 2, 2010.

7,818,705 M. Hutton and D. Lewis.  Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew.  October 19, 2010.

7,812,635 M. Hutton.  Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions.  October 12, 2010.

7,804,325 J. Pistorius and M. Hutton.  Dedicated function block interfacing with general purpose function blocks on integrated circuits.  September 28, 2010.

7,784,008 M. Hutton, D. Karchmer and Z. Zhang.  Performance visualization system.  August 24, 2010.

7,733,124 K. Duwel and M. Hutton.  Method and apparatus for PLD having shared storage elements.  June 8, 2010.

7,724,032 M. Hutton, J. Schleicher and D. Mansur.  Field-programmable gate array with integrated application specific integrated circuit fabric.  May 25, 2010.

7,716,623 T. Vanderhoek, V. Betz, D. Cashman, D. Lewis and M. Hutton.   Programmable logic device architectures and methods for implementing logic in those architectures.  May 11, 2010.

7,705,628 M. Hutton, A. Lee, G. Baeckler, J. Yuan and K. Duwel.  Programmable logic device having logic elements with dedicated hardware to configure look-up tables as registers.  April 27, 2010.

7,689,955 B. van Antwerpen, M. Hutton, G. Baeckler and R. Yuan.  Register retiming technique.  March 30, 2010.

7,675,319 M. Hutton, Programmable logic device having complex blocks with improved logic functionality.  March 9, 2010.

7,671,625 J. Schleicher, R. Yuan, B. Pedersen, S. Kaptanoglu, G. Baeckler, D. Lewis, M. Hutton, A. Lee, R. Saini and H. Kim,  Omnibus logic element.  March 2, 2010.

7,619,443 T. Vanderhoek, V. Betz, D. Cashman, D. Lewis and M. Hutton, Programmable logic device architectures and methods for implementing logic in those architectures.  November 17, 2009.

7,607,118 M. Hutton, Techniques for using edge masks to perform timing analysis.  October 20, 2009.

7,605,603 M. Hutton and A. Lee, User-accessible freeze-logic for dynamic power reduction and associated methods.  October 20, 2009.

7,594,208 K  T. Borer, I. Chesal, J. Schleicher, D. Mendel, M. Hutton, B. Ratchev, Y. Sankar, B. van Antwerpen, G. Baeckler, R. Yuan, S. Brown, V. Betz and K. Chan.  Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage.  Sept 22, 2009.

7,579,866  M. Hutton, D. Cashman, J. Yuan and K. Bozman, Programmable Logic Device with configurable override of region-wide signals.  August 25, 2009.

7,577,929  M. Hutton and D. Karchmer, Early timing estimation of timing statistical properties of placement.  August 18, 2009.

7,545,196  M. Hutton, K. Tharmalingam, Y-W Lin and D. Neto,  Clock distribution for specialized processing block in programmable logic device.  June 9, 2009.

7,538,579  J. Schleicher, R. Yuan, B. Pedersen, S. Kaptanoglu, G. Baeckler, D. Lewis, M. Hutton, A. Lee, R. Saini and H. Kim,  Omnibus logic element.  May 26, 2009.

7,509,618  M. Hutton, Y-Y Hwang and D. Mendel,  Method and apparatus for facilitating an adaptive electronic design automation tool.  Mar 24, 2009. 

7,492,188  T. Ngai, B. Pedersen, S. Shumarayev, J. Schleicher, W-J Huang, M. Hutton, V. Maruri, R. Patel, P. Kazarian, A. Leaver, D. Mendel and J. Park,  Interconnection and input/output resources for programmable logic integrated circuit devices.  Feb 17, 2009. 

7,469,394  M. Hutton and Y. Lin.  Timing variation aware compilation.  Dec 23, 2008.

7,420,390  M. Hutton and J. Schleicher.  Method and apparatus for implementing additional registers in field-programmable gate arrays to reduce design size.  Sept 2, 2008.

7,394,287  M. Hutton.  Programmable logic device having complex logic blocks with improved logic cell functionality.  July 1, 2008.

7,373,631   J. Yuan, G. Baeckler, J. Schleicher and M. Hutton.  Methods of producing application-specific integrated circuit equivalents of programmable logic.  May 13, 2008.

7,368,944  M. Hutton, B. Pedersen, S. Kaptanoglu, D. Lewis and T. Vanderhoek.  Organizations of logic modules in programmable logic devices.  May 6, 2008.

7,368,942  M. Hutton, B. Pedersen and J. Schleicher.  Dedicated resource interconnects.  May 6, 2008.

7,355,442  M. Hutton and S. Kaptanoglu.  Dedicated crossbar and barrel shifter block on programmable logic resources.  Apr 8, 2008.

7,350,176  G. Baeckler and M. Hutton.  Techniques for mapping to a shared lookup table mask.   Mar 25, 2008.  

7,337,100  J. Pistorius, B. van Antwerpen, G. Baeckler, R. Yuan and Y-Y. Hwang, Physical resynthesis of a logic design.  Feb 26, 2008.

7,330,052  S. Kaptanoglu, B. Pedersen, J. Schleicher, J. Yuan, M. Hutton and D. Lewis, Area-efficient fractureable logic elements.  Feb 12, 2008.

7,312,633  M. Hutton and D. Lewis.  Programmable routing structures providing shorter timing delays for input/output signals.  Dec 25, 2007

7,248,072  M. Hutton and V. Betz.   Swap MUX to relieve logic device input stress.   July 24, 2007.

7,181,703  T. Borer, I. Chesal, J. Schleicher, D. Mendel, M. Hutton, B. Ratchev, Y. Sankar, B. van Antwerpen, G. Baeckler, R. Yuan, S. Brown, V. Betz and K. Chan.  Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage.  Feb 20, 2007. 

7,176,718  M. Hutton, B. Pedersen, S. Kaptanoglu, D. Lewis and T. Vanderhoek.   Organizations of logic modules in programmable logic devices.  Feb 13, 2007.

7,167,022  J. Schleicher, R. Yuan, B. Pedersen, S. Kaptanoglu, G. Baeckler, D. Lewis, M. Hutton, A. Lee, R. Saini and H. Kim.  Omnibus logic element including lookup table-based logic elements.  Jan 23, 2007. 

7,135,888  M. Hutton and D. Lewis.  Programmable routing structures providing shorter timing delays for input/output signals.  Nov 14, 2006. 

7,133,819  M. Hutton.  Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices.  Nov 7, 2006. 

7,120,883  B. van Antwerpen, M. Hutton, G. Baeckler and R. Yuan.  Register retiming technique .   Oct 10, 2006. 

7,093,219  M. Hutton.  Techniques for using edge masks to perform timing analysis.  Aug 15, 2006. 

7,080,333  B. Ratchev, M. Hutton and G. Baeckler.  Verifying logic synthesizers.   July 18, 2006. 

7,042,248 M. Hutton and S. Kaptanoglu.  Dedicated crossbar and barrel shifter block on programmable logic resources.   May 9, 2006. 

7,010,777  M. Hutton, A. Lee and R. Saini.   Shared lookup table enhancements for the efficient implementation of barrel shifters.  March 7, 2006. 

6,989,689  T. Ngai, B. Pedersen, S. Shumarayev, J. Schleicher, W-J Huang, M. Hutton, V. Maruri, R. Patel, P. Kazarian, A. Leaver, D. Mendel and J. Park,  Interconnection and input/output resources for programmable logic integrated circuit devices.  Jan 24, 2006. 

6,977,520  M. Hutton and R. Cliff.   Time-multiplexed routing in a programmable logic device architecture.   Dec 20, 2005. 

6,894,533  T. Ngai, B. Pedersen, S. Shumarayev, J. Schleicher, W-J Huang, M. Hutton, V. Maruri, R. Patel, P. Kazarian, A. Leaver, D. Mendel and J. Park.   Interconnection and input/output resources for programmable logic integrated circuit devices.  May 17, 2005. 

6,747,480  S. Kaptanoglu, M. Hutton and J. Schleicher.  Programmable logic device with bidirectional cascades.   June 8, 2004. 

6,429,681  M. Hutton,   Programmable logic device routing architecture to facilitate register re-timing.  Aug 6, 2002.

6,407,576  T. Ngai, B. Pedersen, S. Shumarayev, J. Schleicher, W-J Huang, M. Hutton, V. Maruri, R. Patel, P. Kazarian, A. Leaver, D. Mendel and J. Park.  Interconnection and input/output resources for programmable logic integrated circuit devices.  June 18, 2002.