The 7th Workshop on

Multi-core and Rack Scale Systems

co-located with Eurosys 2017
23 April 2017, Belgrade, Serbia

Submission deadline (extended): February  17th, 2017, 11:59pm (GMT)
Submission website is open!
Author notification: February 27th, 2017


Modern multi-core and accelerator-rich architectures present a variety of challenges for system developers. To achieve high performance on these platforms, application developers will need to exploit parallelism and leverage low-level hardware features to a much greater extent than before. At the same time, these traits are transcending single host systems as emerging integrated fabric technologies enable disaggregated rack-scale system designs in data centers, with hundreds of GB/s, sub-microsecond interconnects blurring traditional machine boundaries.

The workshop (a second year consolidated workshop of the successful SFMA and WRSC) brings together researchers in operating systems, language runtime, virtual machine and architecture communities to present and discuss their system building experiences with the new generations of parallel and heterogeneous hardware.

Topics of interest include (but are not limited to):
  • novel multi-core operating system designs,
  • runtime systems and programming environments for future hardware,
  • OS or runtime support for heterogeneous processing cores,
  • scheduling on many-core architectures,
  • hybrid scale-up/scale-out system designs
  • energy efficiency, fault tolerance and resource management on future multi-core architectures,
  • performance evaluation of potential future hardware,
  • architectural support for systems-level software, and
  • case studies of system-level software design for current or future multi-core hardware.

Confirmed Invited Speakers

We are delighted to host several insightful keynotes about the state-of-the-art and the trends of accelerated computing in data centers. Among the confirmed speakers are:

Dror Goldenberg, VP Software in Mellanox; he will discuss smart networks and network accelerators.

Christoph Hagleitner,  Accelerator Technologies Manager, IBM Zurich; he will talk about new developments in Coherent Accelerator Processor Interface.

Kalin Ovtcharov, Catapult Project, MSR; he will talk about FPGA and accelerators in data centers

Publication policy

The papers will be distributed to workshop participants via the website, but will not be published via ACM Digital Library with the aim  to encourage the submission of early-stage work soliciting feedback from the community. This policy allows  later submission to more formal venues, e.g., EuroSys, OSDI, or ISCA. 

Workshop format

We plan to have 4-6 presentations of accepted papers, and 3 keynote speakers with world-established expertise in the field of interest for the workshop. The workshop will conclude with a panel discussion.

Paper submission

Authors are invited to submit original and unpublished work that exposes a new problem, advocates a specific solution, or reports on actual experience. The submissions are of two types: short papers (5 pages) or position papers (1-2 pages), not  including references.  Papers should be submitted using the standard two-column ACM SIG proceedings or SIG alternate template.  

Submit your papers  here

Paper submission is single-blind.  

For any information, please contact workshop organizers