Research


Low power SoC Design
    
    Low power design has been identified as a key challenge for the commercial success of various mobile devices. 
    Particular interested areas include: clock tree analysis with mix-VT cells in multi-mode multi-corner design scenario, Leakage and PVT control, IR drop induced timing failure.

Interconnect centric design methodology

    It has been widely accepted that as technology scales down, interconnect is becoming the limiting factor of performance and power consumption.
    Particular interested areas include: clock network analysis and optimization, repeated RC wire analysis under different design goals, passive compensation for On-Chip/Off-Chip high speed links.

Global routing Algorithm

    Multi-driven global routing algorithm considering congestion, delay and crosstalk is particularly interested.