3-D Integration Group at NTU

 


CHUAN SENG TAN (FIMAPS, SMIEEE) 

 (陈全胜)

Professor

School of Electrical and Electronic Engineering
Nanyang Technological University
50 Nanyang Avenue, S2-B2c-85
Singapore 639798
Tel: +65-6790-5636

E-mail: tancs@ntu.edu.sg

(updated: November 28, 2019 @Thanksgiving)

 

ACADEMIC QUALIFICATIONS 

Ph.D. in Electrical Engineering and Computer Science, Massachusetts Institute of Technology, USA (2006)

M.Eng. in Advanced Materials, Singapore-MIT Alliance, National University of Singapore, Singapore  (2001)

B.Eng (Hons) in Electrical Engineering, University of Malaya, Malaysia (1999)


AWARDS/HONORS/RECOGNITIONS
Fellow of the Society Award, International Microelectronics Assembly and Packaging Society (IMAPS) - 2019
Distinguished Lecturer, IEEE Electronics Packaging Society (EPS) - 2019-2023
Exceptional Technical Achievement Award, IEEE Electronics Packaging Society (EPS), USA - 2019
RESEARCH INTERESTS

Broadly, the main objective of my research is to explore, identify, and develop enabling technologies for three-dimensional (3D) integration and packaging of future integrated circuits on mature silicon platform in order to maintain performance growth (3-5 years target) as well as to offer functional diversification (>5 years target). This objective is motivated by the non-commensurate return of conventional scaling (“Moore’s Law”) in the semiconductor industry and the imminent need for heterogeneous integration. The specific areas are:

 (1)        Advanced micro-fabrication technology that are scalable and reliable, such as fine pitch solder-less metal bonding and through silicon via (TSV), to enable 3D stacking and interconnection of ultra-thin integrated circuits;

(2)   Direct 3D stacking of integrated circuits and other functional components to realize true heterogeneous integration of materials, devices, and functions.

In addition to 3D integration and packaging, I am also actively engaged in engineered substrate and monolithic 3D integration of group-IV materials including epitaxy, wafer bonding, layer transfer, and devices for silicon photonics applications.


Resume (Updated: Nov 28, 2019)

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