3-D Integration Group at NTU

 


 

CHUAN SENG TAN 

 (陈全胜)

Associate Professor

School of Electrical and Electronic Engineering
Nanyang Technological University
50 Nanyang Avenue, S2-B2c-85
Singapore 639798
Tel: +65-6790-5636

E-mail: tancs@ntu.edu.sg

(updated: February 21, 2014)

 

NEWS and ANNOUNCEMENTS! 

February 21, 2014 - Dr CS Tan is now tenured associate professor at NTU.

November 9, 2013 - Check out our newest chip - a 3D stack of MEMS-CMOS chip for motion sensing http://www.youtube.com/watch?v=zpYXEEsE2_E

August 17, 2013 - If you are interested in PhD study in microelectronics in the areas of 3D IC, advanced substrate or materials/devices, please contact me. I have PhD scholarship for 2014.

August 12, 2013 - Welcome new PhD students: Bao Shuyu, Wei Mengyao, Yashwaant Verrma, Lin Ye. We look forward to working closely with you.

July 31, 2013 - Heartiest Congratulations to the first group of PhD students (Tan Yew Heng, Lim Dau Fatt, Lin Wenhu and Peng Lan), you guys have made it! 

June 15, 2013 - Chuan Seng Tan will serve on the technical committee (interconnections) of IEEE ECTC.


ACADEMIC QUALIFICATIONS 

Ph.D. in Electrical Engineering and Computer Science, Massachusetts Institute of Technology, USA (2006)

M.Eng. in Advanced Materials, Singapore-MIT Alliance, National University of Singapore, Singapore  (2001)

B.Eng (Hons) in Electrical Engineering, University of Malaya, Malaysia (1999)

RESEARCH INTERESTS

Broadly, the main objective of my research is to explore, identify, develop, refine, and verify enabling technology for three-dimensional (3-D) integration and packaging of integrated circuits on mature silicon platform in order to maintain performance growth (3-5 years target) as well as to offer functional diversification in future integrated circuits and systems (>5 years target). This objective is aligned with the “More Moore” and “More than Moore” activities in the semiconductor industry. Specifically, the end goals are three-fold:

 

1)    To invent and develop advanced micro-fabrication technology that are scalable and reliable, such as fine pitch metal bonding and through silicon via, to enable 3-D stacking and interconnection of ultra-thin integrated circuits on a silicon platform;

2)    To utilize the third (i.e. vertical) dimension of integrated circuits for direct placement of IC and non-IC blocks for performance enhancement as well as functional diversification in future micro-systems;

3)    To formulate and develop a “pick, place, and mix” method that enables large area direct sorting, precision placement, and mixing of various layers on silicon platform to realize true heterogeneous integration of materials, devices, and functions. 

In addition to 3D integration and packaging at the interconnect and package levels, I am also actively engaged in monolithic group-IV hetero-structures at the material and substrate levels including epitaxial growth, bonding, transfer, processing, and devices.

Current projects are:

(1) 3D IC packaging and integration - Fine-pitch and high through-put Cu-Cu bonding, through silicon via (TSV), TSV-less CMOS-MEMS stacking;

(2) InP/Si bonding - Surface treatment, precision bonding, thermal characteristics;

(3) Advanced substrate - Ge/Si, GOI, III-V/Ge/Si;

(4) Thermal management of integrated electronics - vapor chamber design, modeling, fabrication and characterization.