High Speed Analog Circuits




High Speed Analog Circuits

Clock generation

  • Low in-band phase noise hybrid domain PLL
  • Low reference spur, low fractional spur digital PLL

  • Reference multiplied, cascaded PLL

  • Supply noise insensitive PLL

  Memory interface

Volatile memory (DRAM) 

  • Quadrature signal corrector for DRAM interface

  • Supply noise immune clock distribution for low-power DRAM


Non-volatile memory (NAND flash memory)

  • Read, Program and Erase time reduction with narrow Cell Vth distribution

  • Low power analog circuit and logic design

Wireline Transceiver
  • high-speed wire-line transceiver for memory interface

  • energy efficient design with noise, ISI and crosstalk immunity
  • signaling schemes (e.g. PAM, PWM), channel equalization, noise-filtering and DSP algorithms in ADC-based detection