About Me

Silicon architecture engineer at Intel 


  • Georgia Institute of Technology, Atlanta, GA
    • Ph.D. in Computer Science, Fall 2009 ~ August 2013
      • Thesis Topic: Shared Resource Management for Efficient Heterogeneous Computing
      • Thesis Advisor: Prof. Hyesoon Kim
    • M.S. in Computer Science, May 2009
    • Graduate courses
  • Sogang University, Seoul, Korea
    • B.S. in Computer Science, February 2007

Work Experience

  • Silicon Architecture Engineer, September 2013 - Present
    MIC Architecture, Intel/PDG, Hillsboro, OR
  • Graduate Research Assistant, 2008 - 2013
    Georgia Institute of Technologoy, Atlanta, GA
  • Graduate Intern Technical, May 2012 - August 2012
    Platform architecture research group, Intel Labs, Intel, Santa Clara, CA
    Manager: Mani Azimi
  • Graduate Intern Technical, May 2011 - August 2011
    Visual and Parallel Computing Group (VPG), Intel, Austin, TX
    Manager: Eric Sprangle


  1. Jaekyu Lee, Dong Hyuk Woo, Hyesoon Kim, and Mani Azimi
    "GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs",
    In IEEE Transactions on Computers (TC), accepted
  2. Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili
    "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture",
    In Journal of Parallel and Distributed Computing (JPDC), Vol. 73, Issue 12, pp. 1525-1538, December 2013
  3. Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili
    "Adaptive Virtual Channel Partitioning for Network-on-Chip in Heterogeneous Architectures"
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, pp.48:1-48:28, October 2013
  4. Jaekyu Lee, Hyesoon Kim, and Richard Vuduc
    "When Prefetching Works, When It Doesn't, and Why"
    An invited paper (originally published in TACO), 8th Int'l Conf. on High-Performance and Embedded Architectures and Compilers (HiPEAC), January, 2013 Slide
  5. Jaewoong Sim, Jaekyu Lee, Moinnuddin Qureshi, and Hyesoon Kim
    "FLEXclusion: Balancing Cache Capacity and On-Chip Traffic with Flexible Exclusion"
    In Proc. of the 39th Int'l Symp. on Computer Architecture (ISCA-39),
    Portland, OR, June, 2012 (acceptance rate 18% (47/262)), to appear
  6. Jaekyu Lee, Hyesoon Kim, and Richard Vuduc
    "When Prefetching Works, When It Doesn't, and Why"
    In ACM Transactions on Architecture and Code Optimization (TACO), Vol. 9, No. 1, pp.2:1-2:29, March 2012
  7. Jaekyu Lee and Hyesoon Kim
    "TAP: A TLP-Aware Cache Management Schemes for a CPU-GPU Heterogeneous Architecture"
    In Proc. of the 18th Int'l Symp. on High Performance Computer Architecture (HPCA-18), pp.91-102
    New Orleans, LA, February, 2012 (acceptance rate 17% (36/210)) Slide
  8. Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin
    "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function"
    IEEE Computer Architecture Letters (CAL), 2011
  9. Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, and Richard Vuduc
    "Many-Thread Aware Prefetching Mechanisms for GPGPU Applications",
    In Proc. of the 43rd Int'l Symp. of Microarchitecture (MICRO-43), pp.213-224
    Atlanta, GA, December, 2010 (acceptance rate 18% (45/248)) Slide
  10. Nagesh B. Lakshminarayana, Jaekyu Lee, and Hyesoon Kim
    "Age Based Scheduling for Asymmetric Multiprocessors",
    SC, pp.25:1-25:12, November, 2009 (acceptance rate 23% (59/261)) Slide


Email: jq dot lee 17 at gmail dot com