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ADC_LPC1768

 Analogue to Digital Conversion with the NXP LPC1768

  1. Introduction to the ADC with the LPC1768
  2. Configuring the power to the ADC
  3. Selecting the ADC Function
  4. Peripheral Clocks for the NXP LPC1768 as used in the MBED board.
  5. The ADC Internal Clock
  6. Selecting and triggering the analogue to digital conversion.
  7. ADC Registers
    1. ADC Global Status Register
    2. ADC Global Data Registers
  8. Appendix: Summary of ADC Registers


  1. Introduction to the ADC with the LPC1768
  2. ../E4140013.jpg

    MBED Application Board showing Poteniometers 1 & 2 used as analogue inputs. The example on this page will use the right hand potentiometer.

    The NXP LPC1768 ADC has 8 multiplexed inputs. (See table below). All 8 inputs are alternate functions to the default digital input-output functions. Pins 98 (P0.2) and 99 (P0.3) are not avalable as external pins on the MBED board. Pins 20 (P1.31) and 21 (P1.30) are wired directly to potentiometers on the application board. Potentiometer 2 (hightlighted) will be used in the following examples on this page.

    Pin No Function 1 Function 2
    Alternate Function 1
    Function 3
    Alternate Function 2
    Function 4
    Alternate Function 3
    MBED Application Board
    6 P0.26 AD0.3 AOUT RXD3 P18 Analogue Out
    7 P0.25 AD0.2 I2SRX_SDA TXD3 P17 Analogue In
    8 P0.24 AD0.1 I2SRX_WS CAP3.1 P16 Switch Right
    9 P0.23 AD0.0 I2SRX_CLK CAP3.0 P15 Switch Up
    20 P1.31 Reserved SCLK AD0.5 Pin 20 Pot 2
    21 P1.30 Reserved VBUS AD0.4 Pin 19 Pot 1
    98 P0.2 TXD0 AD0.7      
    99 P0.3 RXD0 AD0.6      

    NXP LPC 1768 pins with ADC inputs.

    Pictorially this table is illustrated below:

    ../NXP_ADC_2_Pots.gif

    ADC circuitry on MBED system

    As indicated/highlighted Pot 2 is wired to pin 20 of the MBED board. It is channel 5 of the analogue to digital converter - the third alternative function for pin P1.31.

    A more detail pin description including voltage references for the ADC is given below.

    Pin Type Description
    AD0.7 to AD0.0 Input Analog Inputs. The ADC cell can measure the voltage on any of these input signals. Digital signals are disconnected from the ADC input pins when the ADC function is selected on that pin in the Pin Select register.
    Warning: if the ADC is used, signal levels on analog input pins must not be above the level of VDDA at any time. Otherwise, A/D converter readings will be invalid. If the A/D converter is not used in an application then the pins associated with A/D inputs can be used as 5 V tolerant digital IO pins.
    VREFP, VREFN Reference Voltage References. These pins provide a voltage reference level for the ADC and DAC.
    Note: VREFP should be tied to VDD(3V3) and VREFN should be tied to VSS if the ADC and DAC are not used.
    VDDA, VSSA Power Analog Power and Ground. These should typically be the same voltages as VDD and VSS, but should be isolated to minimize noise and error.
    Note: VDDA should be tied to VDD(3V3) and VSSA should be tied to VSS if the ADC and DAC are not used.

    Signals relevant to the LPC1768 ADC


  3. Configuring the power to the ADC
  4. Bit Symbol Description Reset value
    0 - Reserved. NA
    1 PCTIM0 Timer/Counter 0 power/clock control bit. 1
    2 PCTIM1 Timer/Counter 1 power/clock control bit. 1
    3 PCUART0 UART0 power/clock control bit. 1
    4 PCUART1 UART1 power/clock control bit. 1
    5 - Reserved. NA
    6 PCPWM1 PWM1 power/clock control bit. 1
    7 PCI2C0 The I2C0 interface power/clock control bit. 1
    8 PCSPI The SPI interface power/clock control bit. 1
    9 PCRTC The RTC power/clock control bit. 1
    10 PCSSP1 The SSP 1 interface power/clock control bit. 1
    11 - Reserved. NA
    12 PCADC A/D converter (ADC) power/clock control bit. 0
    13 PCCAN1 CAN Controller 1 power/clock control bit. 0
    14 PCCAN2 CAN Controller 2 power/clock control bit. 0
    15 PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. 1
    16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0
    17 PCMCPWM Motor Control PWM 0
    18 PCQEI Quadrature Encoder Interface power/clock control bit. 0
    19 PCI2C1 The I2C1 interface power/clock control bit. 1
    20 - Reserved. NA
    21 PCSSP0 The SSP0 interface power/clock control bit. 1
    22 PCTIM2 Timer 2 power/clock control bit. 0
    23 PCTIM3 Timer 3 power/clock control bit. 0
    24 PCUART2 UART 2 power/clock control bit. 0
    25 PCUART3 UART 3 power/clock control bit. 0
    26 PCI2C2 I2C interface 2 power/clock control bit. 1
    27 PCI2S I2S interface power/clock control bit. 0
    28 - Reserved. NA
    29 PCGPDMA GPDMA function power/clock control bit. 0
    30 PCENET Ethernet block power/clock control bit. 0
    31 PCUSB USB interface power/clock control bit. 0

    Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description

    Following reset the PCADC (Power Clock Control Bit to ADC) bit is cleared and the ADC is disabled. The first step is to set PCADC followed by PDN in ADC0CR. (See brief description below)

    (Note: The PDN bit in the ADCR must be cleared before clearing this PCADC, and PCADC set before setting PDN.)

    Bit Symbol Description Reset value
    7:0 SEL Selects which of the AD0.7:0 pins is (are) to be sampled and converted. 0x01
    15:8 CLKDIV The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter. 0
    16 BURST 1 The AD converter does repeated conversions at up to 200 kHz 0
    20:17 - Reserved, user software should not write ones to reserved bits. NA
    21 PDN 1 The A/D converter is operational. 0 The A/D converter is in power-down mode. 0
    23:22 - Reserved, user software should not write ones to reserved bits. NA
    26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 000
    27 EDGE 1 Start conversion on a falling edge. 0 Start conversion on a rising edge. 0
    31:28 - Reserved, user software should not write ones to reserved bits. NA

    A/D Control Register (ADCR - address 0x4003 4000) brief bit description

    The ADC Control Register will be used in many steps of the ADC operation.
    The ADCR bit description will be repeated as required expanding the explanation of the bits of interest.

    Example: Give the code to enable power the ADC.

    Possible Solution:

    LPC_SC->PCONP |= 1<<12;            //power to ADC
    LPC_ADC->ADCR |= 1<<21;            //turn on power for ADC


  5. Selecting the ADC Function
  6. ../NXP_IOPIN.gif

    Simplified block diagram of NXP LPC1768 input-output pin.

    As illustrated the function of the input-output pin is selected using the PINSEL register which is attached to the pin control block (PINCON). PINSEL0 and PINSEL1 select/control the pins of Port 0, PINSEL2 and 3 select/controls port 1 etc. Following reset the PINSEL registers are cleared so the pin is attached to the GPIO function.

    Each pin is controlled by 2 bits in the PINSEL register. PINSEL0[1:0] controls PIN P0.0, PINSEL0[3:2] controls PIN P0.1. PINSEL0[31:30] controls PIN P0.15, PINSEL1[1:0] controls PIN P0.16, PINSEL2[1:0] controls PIN P1.0 etc.- PSEL3[31:30] will control PIN P1.31

    For this page the ADC will be AD0.5 attached to pin P1.31. See Introduction to the ADC with the LPC1768. The following code will select alternate function 3 (AD0.5) for pin P1.31:

    LPC_PINCON->PINSEL3 |= 0x03<<30;      //Pin P1.31 allocated to alternate function 3

    Selecting the ADC function the pull up/down resistors should be disabled via the Pin Mode registers illustrated in the figure below.

    ../NXP_GPIO_003.gif

    Address map for the LPC1768 Pin Mode registers.

    In this example pin P1.31 is used as the ADC input. See Introduction to the ADC with the LPC1768. The following code will disable the resistors for pin P1.31:

    LPC_PINCON->PINMODE3 |= 0x02<<30;      // Pull up/down on Pin P1.31 disabled


  7. Peripheral Clocks for the NXP LPC1768 as used in the MBED board.
  8. The following discussion will assume that the main clock for the LPC1768 has been programmed.

    Each LPC1768 peripheral including the ADC has a clock derived from the main clock as illustrated.

    ../NXP_Periheral_CLK.gif

    Peripheral Clock Divider

    As shown in the figure the frequency of the peripheral clock is determined by two bits in the PCLKSEL registers (PCLKSEL0 which includes the ADC is shown below). Following reset PCLKSEL0/1 are both cleared which sets the peripheral clock frequency to CCLK/4.

    With the NXP LPC1768 the peripheral clocks are always active. The user will have a choice of frequency determined by two bits in one of the two peripheral clock selection registers PCLKSEL0 and PCLKSEL1. By default at reset all values are 00 ie CCLK/4.

    00 PCLK_peripheral = CCLK/4
    01 PCLK_peripheral = CCLK
    10 PCLK_peripheral = CCLK/2
    11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2,
    and CAN filtering when “11” selects = CCLK/6.

    Peripheral Clock Selection register bit values PCLKSEL0 and PCLKSEL1.

    Bit Symbol Description
    1:0 PCLK_WDT Peripheral clock selection for WDT.
    3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0.
    5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1.
    7:6 PCLK_UART0 Peripheral clock selection for UART0.
    9:8 PCLK_UART1 Peripheral clock selection for UART1.
    11:10 - Reserved.
    13:12 PCLK_PWM1 Peripheral clock selection for PWM1.
    15:14 PCLK_I2C0 Peripheral clock selection for I2C0.
    17:16 PCLK_SPI Peripheral clock selection for SPI.
    19:18 - Reserved.
    21:20 PCLK_SSP1 Peripheral clock selection for SSP1.
    23:22 PCLK_DAC Peripheral clock selection for DAC.
    25:24 PCLK_ADC Peripheral clock selection for ADC.
    27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1]
    29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1]
    31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering.[1]

    Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit description

    Example: Set the peripheral clock for the ADC to the system clock frequency (CCLK).

    Solution:      LPC_SC-&GT;PCLKSEL0 |= 1<<24;       //pclk = cclk


  9. The ADC Internal Clock
  10. ../CLK_Div1768.gif

    ADC Clock Divider Chain

    As illustrated the micro-controller clock will have been through 3 dividers by the time it reaches the ADC. The first divider determines the system clock and is applicable for the LPC1768 as a whole. Each peripheral has a clock divider discussed in the previous section and finally there is the divider that is part of the ADC Control Register shown below.

    Bit Symbol Description Reset value
    7:0 SEL Selects which of the AD0.7:0 pins is (are) to be sampled and converted. 0x01
    15:8 CLKDIV The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock
    for the A/D converter, which should be less than or equal to 13 MHz. Typically,
    software should program the smallest value in this field that yields a clock of 13 MHz or slightly
    less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
    0
    16 BURST 1 The AD converter does repeated conversions at up to 200 kHz 0
    20:17 - Reserved, user software should not write ones to reserved bits. NA
    21 PDN 1 The A/D converter is operational. 0 The A/D converter is in power-down mode. 0
    23:22 - Reserved, user software should not write ones to reserved bits. NA
    26:24 START Start conversion 000
    27 EDGE 1 Start conversion on a falling edge. 0 Start conversion on a rising edge. 0
    31:28 - Reserved, user software should not write ones to reserved bits. NA

    Clock Division Bits in A/D Control Register (ADCR - address 0x4003 4000)

    Example: In the test program the internal clock has been used as the system clock. Since this is less than 13MHz it may be used directly to the ADC. For illustrative purposes the sysyem clock will be divided by 2. The sample code will be:

    LPC_SC->PCLKSEL0 |= 1<<24;      //pclk = cclk - as previous
    LPC_ADC->ADCR &= ~0xFF00;       //Default divide by 1
    LPC_ADC->ADCR |= 1<<8;       // divide by 2


  11. Selecting and triggering the analogue to digital conversion.
  12. Once configured the operation of the ADC will be controlled by the ADC Control Register. See below:

    Bit Symbol Description Reset value
    7:0 SEL Selects which of the AD0.7:0 pins is (are) to be sampled and converted. 0x01
    15:8 CLKDIV The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter. 0
    16 BURST 1 The AD converter does repeated conversions at up to 200 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed. Remark: START bits must be 000 when BURST = 1 or conversions will not start. Conversions are software controlled and require 65 clocks. 0
    20:17 - Reserved. NA
    21 PDN 1 The A/D converter is operational. 0 The A/D converter is in power-down mode. 0
    23:22 - Reserved. NA
    26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
    000 No start (this value should be used when clearing PDN to 0).
    001 Start conversion now.
    010 Start conversion when the edge selected by bit 27 occurs on the P2.10 / EINT0 / NMI pin.
    011 Start conversion when the edge selected by bit 27 occurs on the P1.27 / CLKOUT / USB_OVRCRn / CAP0.1 pin.
    100 Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin.
    101 Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin.
    110 Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin.
    111 Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin.
    000
    27 EDGE This bit is significant only when the START field contains 010-111. In these cases: 1 Start conversion on a falling edge on the selected CAP/MAT signal. 0 Start conversion on a rising edge on the selected CAP/MAT signal. 0
    31:28 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

    A/D Control Register (ADCR - address 0x4003 4000) bit description

    Notes: 1. If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection logic.

    2. Once an ADC conversion is started, it cannot be interrupted. A new software write to launch a new conversion or a new edge-trigger event will be ignored while the previous conversion is in progress. For the neophyte there are two possible choices:

    1. Set the BURST bit to 0 and program the START (001) for each reading.
    2. Allow continuous readings by clearing the START bits and setting BURST to 1.

    Example Select channel 5 and start (trigger) the ADC conversion.

    Possible Solution

    LPC_ADC->ADCR &= ~(1<<16);      //ensure burst mode is off
    LPC_ADC->ADCR &= ~(7<<24);       //do not start yet
    LPC_ADC->ADCR |= 1<<5;       //select channel 5
    while (1)       //multiple readings
    {
          LPC_ADC->ADCR |= 1<<24; //start pulse
              //take the readings
    }


  13. ADC Registers
  14. Individual Data Registers : For the NXP LPC1768 each channel contains a data register that includes both the status and the reading for that channel. This is illustrated below:

    Bit Symbol Description Reset value
    3:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA
    15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. NA
    29:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA
    30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. 0
    31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. 0

    ADC Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) bit description


    ADC Status Register In addition to the individual data registers the ADC contains a global status registers that contains the status of all channels. This register is shown for completeness below.

    Bit Symbol Description Reset value
    0 DONE0 This bit mirrors the DONE status flag from the result register for A/D channel 0. 0
    1 DONE1 This bit mirrors the DONE status flag from the result register for A/D channel 1. 0
    2 DONE2 This bit mirrors the DONE status flag from the result register for A/D channel 2. 0
    3 DONE3 This bit mirrors the DONE status flag from the result register for A/D channel 3. 0
    4 DONE4 This bit mirrors the DONE status flag from the result register for A/D channel 4. 0
    5 DONE5 This bit mirrors the DONE status flag from the result register for A/D channel 5. 0
    6 ONE6 This bit mirrors the DONE status flag from the result register for A/D channel 6. 0
    7 DONE7 This bit mirrors the DONE status flag from the result register for A/D channel 7. 0
    8 OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. 0
    9 OVERRUN1 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. 0
    10 OVERRUN2 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. 0
    11 OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. 0
    12 OVERRUN4 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. 0
    13 OVERRUN5 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. 0
    14 OVERRUN6 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. 0
    15 OVERRUN7 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. 0
    16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags
    is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
    0
    31:17 - Reserved, user software should not write  

    ADC Status register (AD0STAT - address 0x4003 4030) bit description

    ADC Global Data Register : The ADC Global Data Register contains the status, result and the channel number of the last converesion. This register is shown for completeness below.

    Bit Symbol Description Reset value
    3:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA
    15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. NA
    23:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA
    26:24 CHN These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). NA
    29:27 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA
    30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. 0
    31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. 0

    ADC Global Data Register (AD0GDR - address 0x4003 4004) bit description

    Example: Monitor the status for channel 5 and when complete read the result.

    Solution

    while (1)
         {
    LPC_ADC->ADCR |= 1<<24; //start pulse
    while (!(LPC_ADC->ADDR5 & (1<<31)));     //wait
    res = (LPC_ADC->ADDR5);
    res = res &0xFFF0;
    res = res >> 4;
         }


  15. Appendix: Summary of ADC Registers
  16. A summary of the ADC registers is given below. Note both the status and the result are contained in several registers. There is a general or global data register ADGDR that contains the result of the last channel converted and also a specific data register ADDRx which gives the result of the last conversion of channel x. Also ADDRx (and ADGDR) contain the status of the conversion of channel x while the global status register ADSTAT contains the status of all channels.

    Symbol Generic Name Description Access Reset value AD0 Name & Address
    ADCR A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. R/W 1 ADCR - 0x4003 4000
    ADGDR A/D Global Data Register. This register contains the ADC’s DONE bit and the result of the most recent A/D conversion. R/W NA AD0GDR - 0x4003 4004
    ADINTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. R/W 0x100 AD0INTEN - 0x4003 400C
    ADDR0 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. RO NA AD0DR0 - 0x4003 4010
    ADDR1 A/D Channel 1 Data Register. This register contains the result of the most recent conversion completed on channel 1. RO NA AD0DR1 - 0x4003 4014
    ADDR2 A/D Channel 2 Data Register. This register contains the result of the most recent conversion completed on channel 2. RO NA AD0DR2 - 0x4003 4018
    ADDR3 A/D Channel 3 Data Register. This register contains the result of the most recent conversion completed on channel 3. RO NA AD0DR3 - 0x4003 401C
    ADDR4 A/D Channel 4 Data Register. This register contains the result of the most recent conversion completed on channel 4. RO NA AD0DR4 - 0x4003 4020
    ADDR5 A/D Channel 5 Data Register. This register contains the result of the most recent conversion completed on channel 5. RO NA AD0DR5 - 0x4003 4024
    ADDR6 A/D Channel 6 Data Register. This register contains the result of the most recent conversion completed on channel 6. RO NA AD0DR6 - 0x4003 4028
    ADDR7 A/D Channel 7 Data Register. This register contains the result of the most recent conversion completed on channel 7. RO NA AD0DR7 - 0x4003 402C
    ADSTAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag. RO 0 AD0STAT - 0x4003 4030
    ADTRM ADC trim register.   R/W 0x0000,0F00 AD0TRM - 0x4003 4034

    ADC Register Summary.


Generated by John Kneen RMIT University Tuesday, April 15, 2014

RMIT University: Melbourne, Ho Chi Minh, Hong Kong.

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