Jessica H. Tseng


 
email: jhtseng AT gmail DOT com

I have been a Research Staff Member at IBM T. J. Watson Research Center since September 2006.  My main research interests are multi-core processor design, energy-efficient architecture, performance and power modeling, FPGA prototyping, and VLSI design.  I have a B.S. in Electrical Engineering from the University of Florida, Gainesville, a M.S. in Electrical Engineering and Computer Science from Massachusetts Institute of Technology and a Ph.D. in Electrical Engineering and Computer Science, also from Massachusetts Institute of Technology.  Previously at MIT, I was a student member of the Computer Science and Artificial Intelligence Laboratory and was working on the SCALE project which is investigating advanced architectures for energy-efficient high-performance computing with Professor Krste Asanović.  


Publications and Talks

Many of these papers are copyright of the respective journal or conference organizing body.
These online copies are provided for your personal research use only.

  • "IBM PowerPC Design in Bluespec"
    (abstract and PDF paper
    Kattamuri Ekanadham, Jessica Tseng, and Pratap Pattnaik
    IBM Research Technical Report RC24706, December 2008.
  • "Performance Studies of Commercial Workloads on a Multi-core System"
    (PDF paper
    Jessica H. Tseng, Hao Yu, Shailabh Nagar, Niteesh Dubey, Hubertus Franke, Pratap Pattnaik, Hiroshi Inoue, Toshio Nakatani
    2007 IEEE International Symposium on Workload Characterization, Boston, MA, September 2007.  
  • "RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture"
    (PDF paper)
    Jessica H. Tseng and Krste Asanović
    MIT CSAIL Technical Report MIT-CSAIL-TR-2006-066, September 2006.
  • "Banked Microarchitectures for Complexity-Effective Superscalar Microprocessors"
    (PDF thesis)
    Jessica H. Tseng
    Ph.D. Thesis, Massachusetts Institute of Technology, May 2006.
  • "A Speculative Control Scheme for an Energy-Efficient Banked Register File"
    (PDF paper)
    Jessica H. Tseng and Krste Asanović
    IEEE Transactions on Computers, 54(6):741-751, June 2005.
  • "Banked Register Files for SMT Processors"
    (PDF abstract)
    Jessica H. Tseng and Krste Asanović
    Boston Area Architecture Workshop (BARC2004), Boston, MA, January 2004.
  • "Banked Multiported Register Files for High-Frequency Superscalar Microprocessors"
    (PDF paper)
    Jessica H. Tseng and Krste Asanović
    30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003.
  • "Energy-Efficient Register Access"
    (PDF paper)
    Jessica H. Tseng and Krste Asanović
    XIII Symposium on Integrated Circuits and System Design (SBCCI2000), Manaus, Amazonas, Brazil, September 2000.
  • "Energy-Efficient Register File Design"
    (PDF thesis)
    Jessica H. Tseng
    S.M. Thesis, Massachusetts Institute of Technology, December 1999.