The energy costs of a computer architecture matters. It determines the battery life of mobile devices and the performance of power constrained devices like smart phones and data centers.
Examining the fundamental properties of modern computer architectures, you see that in order to have high arithmetic performance you will need to execute many thousands of arithmetic operations per global off-chip memory operation. This is because a memory operation can be more than three orders of magnitude more energy expensive than an arithmetic operation. In this sense you need an algorithm with high compute to bandwidth ratios. As the cost of storing the working set on-die can be similarly expensive, these algorithms need significant locality and a small working set.
My thesis work focused on how we can use a virtual machine model to describe a space of extreme locality algorithms common to computer vision and image processing that are composed of stencil kernels. Stencil kernels are a class of operation (e.g., convolution) in which a given pixel within an output image is calculated from a fixed- size sliding window of pixels in its corresponding input image. These kernels derive their hi locality from the data re-use that occurs in that sliding windows. While such a framework could be used to generate efficient CPU code, my thesis explored how efficient fixed function hardware could be generated from these descriptions.
My current work uses this virtual machine framework to examine the implementation of more flexible architectures that retain much of the efficiency of the fixed function implementation while allowing for run-time programmability. The problems in the space are fundamentally a software-hardware co-design problem where we must demonstrate that the architecture is both practical and efficient. For example, such a system must have a reasonable and effective compiler with an ability to easily/statically examine performance and power of an application.
PhD Thesis, Stanford University, 2015.
J Hegarty, JS Brunhaver, Z. DeVito, J. Ragan-Kelley, N. Cohen, S. Bell, A. Vasilyev, M. Horowitz, P. Hanrahan
SIGGRAPH, 2014 41st International Conference and Exhibition on Computer Graphics and Interactive Techniques, 2014
S Galal, O Shacham, JS Brunhaver, J Pu, A Vassiliev, M Horowitz
Computer Arithmetic (ARITH), 2013 21st IEEE Symposium on, 25-34, 2013
O Shacham, S Galal, S Sankaranarayanan, M Wachs, JS Brunhaver, A Vassiliev, W. Qadeer, S. Sankaranarayanan, A. Vassiliev, S. Richardson, M. Horowitz
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, 623-629, 2012
JS Brunhaver, K Fatahalian, P Hanrahan
Proceedings of the Conference on High Performance Graphics, 1-9, 2010
JS Brunhaver, MD Pant
Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on, 976-979, 2007
Spring 2016 -- EEE 333 Hardware Design
Fall 2015 -- EEE 425 Digital Systems and Circuits
Spring 2015 -- EEE 525 VLSI Design