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Cadence

NOTE!!!  CLICK ON IMAGES FOR A MORE DETAILED VIEW.  Work in progress, feel free to add comments and suggestions how I may improve this page, and references on bottom off this page or email me at stblock@gmail.com (EMAIL SUBJECT:  WEBPAGE SUGESTIONS)

  • Quick CMOS overview [link]
  • GETTING STARTED <CLICK HERE>
  • Creating new library [link]
    • Attaching a existing library to a different technology file
      • Virtuoso screen -> Tools -> Technology File Manager...
      • Under the Technology Tool Box Click on Attach...
      • Next select the library you want to attach and to what technology file and press ok (see image bellow)

  • Creating a VerilogA File [link]
  • Testing a Verilog FILE using Verilog-XL simulator and SimVision [vid]
  • Creating new Schematic [link]
    • Creating Parameters for a Schematic Symbol [link]
    • Hot Keys while in Schematic Editor [link] (I'll post how to edit this later)
Note: These are my current configuration, yours might be slightly different
i                component browser
w              wire
c               copy
m              move
q               edit object properties
l                (lower case L) create net name
f                focus view
9               check nets with probe (highlights connected nets)
ctrl+9        removes probes
shift+x      decends 1 level of hyerarcy
b              accends 1 level of hyerarcy
shift+b      accends to most top level
u              undo
ctrl+scrole buttom -> zoom in and out
right click -> to zoom in on selected section
r               rotate object
p              add pin (input/output/inout)
    • Creating a bus output[link]
    • Creating new symbol [link]
    • Selecting Schematic Parts [link]
    • Changing the properties of more than one object at once [link
  • Creating a functional circuit [link] (for digital and mixed signal testing) 
  • Creating new category [link]
  • V* method for design (still learning... adding notes as I go) [link]
  • SIMULATION
    • CMOS not linked to a technology library [vid]
    • Analog Simulation [link
      • Parametric Sweep
        • Under the Virtuoso window (ADE Window)
          • Tools ---> Parametric Analysis ... 
        • Also under Virtuoso window to view results from Parametric Sweep
          • Tools ---> Results Browser ...
      • EEC119 Senior Mixed Signal Design
        • OPAMP and Bandgap reference example [vid0,vid1,vid2]
          • Vid0 ---> Band Gap and Opamp
          • Vid1 ---> More details from simulation of Opamp
          • Vid2 ---> Miller Compensation of Opamp
    • Mixed Simulation [link]
    • Conversion aid [link]
    • OCEAN SCRIPT [link]
    • Monte Carlo Simulation [link
    • Exporting Data to Matlab [link(under construction)
    • Plotting [link(under construction)
    • Parametric sweep [link0,link1]
    • Saving Operating Points [link]
  • LAYOUT
  • Importing a GDS file (this is a layout file) [link]
  • Exporting a GDS file [link]
  • Simulating Extracted view
  • Creating a Capacitor [EEC_119_version,Poly_Poly_version]
  • Important Hot Keys
    "F3 - incredibly important hotkey. If you hit a hotkey (say "p") and then hit F3 immediately afterwards, it brings a pop-up window detailing all the options associated with that particular hotkey." [link]
  • Note: These are my current configuration, yours might be slightly different
    i                component browser, used to bring in layout of another instance
    ctrl + f       hides instance content
    shift + f      shows instance content
    shift+z        zoom out
    z                zoom in w/ mouse control 
    ctrl + z       zoom in
    f                fitted zoom
    k               ruler
    shift + k     hides ruler
    u               undo
    r               rectangle
    s               stretch
    c               copy
    m              move
    p               (select layer first) creates a path (wires)
    ctrl + a      select all
    ctrl + right click    removes a selected item 
    shift + right click   adds a selected item 
    vias & pins are located under "Create
    l                label
    q               modifies properties of a non-flatten cell
    shift + r over a rectangle to add more rectangles to it

will add more later... like layout stuff :)

References:
  • UCDavis EEC 216 Low Power Digital IC under Dr. Amirtharajah (course material internal)
  • Texas Tech ECE 5321 Analog IC design under Dr. Li (course material internal)
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