Development history

 
The 'Interface 1bis for the Sinclair ZX Spectrum
48k' ('IF1bis') is intended to be a functional substitute for the 'ZX Interface 1'® of Sinclair Research Ltd, providing the host machine with similar storage and communication capabilities, yet on a quite different hardware platform.
Nevertheless, because the:
- 'shadow ROM' paging mechanism for extending
the BASIC interpreter, the
- 'extended BASIC' syntax, the
- 'hook-code' method of accessing 'shadow ROM'
functions, the
- system variables and
- channel descriptors
are all the same as the original’s, full software compatibility is ensured at BASIC and 'hook code' level, for the supported hardware devices.

As the 'IF1bis' was constantly developed since 1994, four different versions were built, which besides sharing the same operating system have little more in common than:
- absence of read-only memory,
- absence of hardware traps,
- spare memory configured as RAM drives.
 
 

  1994 – Version 1a

The first version was designed as an expandable interface, with a four-slot backplane, fully buffered system bus and own voltage regulator, all fitted in a modified Atari GameSelex® case.
The actual 'IF1bis', built on an Apple II proto-typing card, from standard logic ICs, has following specifications:
Memory:
- One 32, 128 or 512 Kbyte SRAM chip with
industry-standard non-volatile controller
Storage:
- Three 128 Kbyte (256-sector) RAM drives
Peripheral ports:
- 'Centronics' parallel printer,
- 'Kempston' joystick.
Operating system:
- 'Shadow ROM' compatible with the Sinclair
'ZX Interface 1'®, except for the 'ZX Net' and
RS-232 functions.
- ESC/P 32/64-columns printer driver integrated
in the ‘BASIC ROM’.


  1998 – Version 1b

- A PIO-mode IDE controller, using the A8 address line to differentiate between first and second byte of 16-bit I/O operations, built on a separate (trimmed ISA XT prototyping) card, from standard logic ICs, was added to the interface.
- A 16-bit FAT-based hard-disk files system was devised to be suitable for an 8-bit processor by way of limiting the size of logical ‘Microdrives’ to 32 Mbyte (65536 sectors), thus avoiding 32-bit arithmetic. Compatibility with the syntax and data structures of the original 'ZX Interface 1'® could still be maintained, using the upper bytes of the system variables D_STRx, and N_STRx, which should always be zero, for storing the path length and respectively the 'file type' along with the first three header-block preamble bytes at offset 28-30 of M-channel descriptors for the 'file type', upper byte of record number and 'device code'.
- Direct file transfer between the interface and external data sources was made possible by including in the 'shadow ROM' a parallel port nibble-mode communication driver and a remote file system for client-server networking, which allows using disk space on a machine running a suitable sever applet, as one 'Microdrive' of unlimited size.


  2002 – One-chip IDE controller

In preparation of further development, a 36-macro-cell CPLD was programmed to act as a one-chip IDE controller for Z80-based systems.

 

  2004 – Version 2a

Incorporating the logic circuitry in one 72-macro-cell CPLD reduced the size of the interface to the extent that it could fit on half a eurocard 3U, inside a Multicomp MB3 box, while retaining the same functionality.


  2005 – 2008 Versions 2b – 2e

The operating system’s memory layout was optimized to the current configuration:
- 'Shadow ROM': 0000-2DFF
- Work area: 2E00-2FFF
- Sector buffers: 3000-3FFF


  2009 – Version 2f

Five input lines were added to the printer port, in place of ground wires, so that it can also function as a streaming parallel port, with 8 input, 8 output and 4 control signals.


  2009 – Parallel port (PP) peripheral

- A MCU-based add-on device was designed to plug into the parallel port of the interface and provide:
a RS-232, a full-speed USB device and a 12-MHz SPI port.
- The parallel port communication driver was adapted accordingly and the assembly language, DOS-interrupt based server applet was transcribed to C and Windows API functions.


  2010 – SD card support

- A SD card socket was attached to the SPI port of the PP peripheral module.
- The common file system for hard drive and SD card was enhanced by implementing allocation unit sizes other than 1 sector/cluster: 2, 4, 8 and 16.


  2010 – System bus (SB) peripheral

As a suitable MCU model became available, a new peripheral module was designed, connected directly to the system's data bus and featuring:
- 12 MHz SPI port with micro-SD card socket,
- full-speed USB device port,
- 'Kempston' joystick port,
- 'Kempston' mouse over PS/2 port.
 

2010 - Version 2g - Version 2i

Control of the SB peripheral module was improved.
 

2011 – Version 3a

A convenient solution was found for an 'internal' version of the interface, housed, together with a hard disk, in a dk’tronics® keyboard case.
- The parallel and joystick ports of the previous design were eliminated, resulting in a smaller 'base board', connected directly to the CPU socket and a SB peripheral module.
- To make sufficient headroom for a wedge-cable, the heat sink was removed and, at the same occasion, the (anyway malfunctioning) onboard power circuits of an issue 3B ZX Spectrum 48k were replaced with a four-pin connector for an external -12V, +5V and +12V supply.
- The SB peripheral board was attached to an aluminum plate, exposing its micro-SD card socket and mini-USB connector, on the right side of the case.


2012 – Version 4a

Aiming at a model suited for small-scale production, the IDE port was eliminated, allowing a simplified test prototype to be built, based on a smaller, 36-macrocell CPLD.
 

2013 - Version 4b

As a further rationalization step, the RAM drive feature was dropped, in order to reduce the non-volatile SRAM size to the actually necessary 32 KBytes and free up six CPLD I/O lines.
On the other hand, a supply voltage monitoring circuit was added, to protect the non-volatile SRAM contents at power-off.
The resulted design, laid out on a 100 x 49.5 mm, two sided PCB, meets the conditions for a feasible (home-) production model.
The first version 4b units were assembled in January and performed according to expectations.