Call for Papers - Special Issue on Dark Silicon

Guest Editors:  Michael Taylor and Steven Swanson (UCSD)

Submissions due:  March 8, 2013
Publication date:    Sept-Oct 2013

Over the last five years, the phenomenon known as Dark Silicon has emerged as the most fundamental factor that shapes our ability to exploit the exponentially increasing resources that Moore’s Law provides. Dark Silicon refers to the exponentially increasing number of a chip’s transistors that must remain passive, or “dark”, in order to stay within a chip’s power budget.

Due to the breakdown of Dennard Scaling, multicore chips will not be able to scale with die area; the fraction of a chip that can be filled with cores running at full frequency is dropping exponentially with each process generation. This reality will force designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim – either idle or significantly underclocked.  As exponentially larger fractions of a chip’s transistors become dark transistors, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift calls for new architectural techniques that “spend” silicon area to “buy” energy efficiency, or for new circuit technologies that overcome the inherent limitations of CMOS that lead to dark silicon. To this end, this IEEE Micro issue seeks original papers on all topics related to dark silicon that span the spectrum of layers in the system stack, from device, circuit and architecture design to the role of software in maximize computing capabilities in the face of dark silicon.

Areas of interest include, but are not limited to:

  • Approaches that offer new insight into the dark silicon problem
  • Architectural approaches to managing and exploiting dark silicon
  • Scalable design and synthesis techniques for customizable and specialized cores
  • Promising Beyond-CMOS approaches that enable post-Dennardian circuit scaling
  • Novel applications for idle chip area
  • Software systems for adapting to dark silicon
  • Power management techniques for dark silicon
  • Energy/power-efficient circuit designs and memory systems for dark silicon
 
Submission procedure:
Please log onto IEEE CS Manuscript Central (https://mc.manuscriptcentral.com/micro-cs) to submit your manuscript to the "Dark Silicon" issue.  Please direct questions to the IEEE Micro magazine assistant (micro-ma@computer.org).  For the manuscript submission, acceptable file formats include Microsoft Word and PDF.  Manuscripts should not exceed 5,000 words including references, with each average-size figure counting as 150 words toward this limit.  Please include all figures and tables, as well as a cover page with all the relevant author contact information (name, postal address, phone, fax, and e-mail address) and a 200-word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication. Accepted articles will be edited for structure, style, clarity, and readability. For more information, please visit the IEEE Micro Author Center (http://www2.computer.org/portal/web/peerreviewmagazines/acmicro)

Important dates:
Initial submissions due:    March  8, 2013
Author notification:          April 30, 2013
Final version due:           June  14, 2013
Publication timeframe:     Sept-Oct, 2013

Questions:
For any further information and questions please contact Guest Editor, Michael Taylor (mbtaylor@ucsd.edu).
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