Publications

International Journals 

Soyeon Joo and SoYoung Kim, “Output-capacitor-free LDO design methodologies for high EMI immunity,” IEEE Transactions on Electromagnetic Compatibility, pp. 497-506, vol. 60, no. 2,  April 2016

Soyeon Joo and SoYoung Kim, “PSR enhancement techniques for output-capacitor-free LDO regulator design,” Analog Integr. Circ. Sig. Process, vol. 93, no. 2, pp. 319-327, Oct. 2017.


Soyeon Joo, Jintae Kim, and SoYoung Kim, "Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs," IEICE Transactions on Electronics Vol. E100-C, No. 5, pp. 504-512, May 2017

JungHun Kim, Hai Au Huynh, and SoYoung Kim, "Modeling of FinFET Parasitic Source/Drain Resistance With Polygonal Epitaxy ," IEEE Transactions on Electron Devices, pp.2072-2079, VOL. 64, NO. 5, MAY 2017

Hai Au Huynh, Jeong-Min Jo, Wansoo Nah, SoYoung Kim, "EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design," IEEE Transactions on Electromagnetic Compatibility, pp. 1-13, vol. 53, no. 10,  Oct 2016

Ikchan Jang, Yoonmyung Lee, SoYoung Kim, Jintae Kim, "Power-Performance Tradeoff Analysis of CML-based High-Speed Transmitter Designs using Circuit-Level Optimization," IEEE Transactions on Circuit and Systems - I, pp. 540-550, vol. 63, no. 4, April 2016

JinHyuk Jeong, Ho Lee, DongHae Kang, and SoYoung Kim, "Gate Engineering to Improve Effective Resistance of 28-nm High-k Metal Gate CMOS Devices," IEEE Transactions on Electron Devices, pp.259-264, vol.63, no.1, Jan. 2016

KyungSoo Kim and SoYoung Kim," Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold Circuits," IEEE Transactions on Electromagnetic Compatibility, pp.963-972, vol. 57, no. 5, Oct. 2015

Bo Pu, Kwang Ho Kim, SoYoung Kim and Wansoo Nah, "Modeling and Parameter Extraction  of Coplanar Symmetrical Meander Lines," IEEE Transactions on Electromagnetic Compatibility, pp. 375-383, vol. 57, no.3, June 2015 

Hee Kwon Lee, Soojung Ryu, Seungbae Lee, SoYoung Kim and Wansoio Nah, "Electromagnetic Field Interference on Transmission Lines due to On-board Antenna,"  International Journal of Antennas and Propagation, vol. 2015, Article ID 104506, 12 pages, 2015. http://dx.doi.org/10.1155/2015/104506

Hai Au Huynh, Hak-Tae Lee, Wansoo Nah, and SoYoung Kim, "Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods," International Journal of Antennas and Propagation, vol. 2015, Article ID 497647, 11 pages, 2015. doi:10.1155/2015/497647.

Ikchan Jang, Jintae Kim and SoYoung Kim, " Accurate delay models of CMOS CML circuits for design optimization," Analog Integrated Circuits and Signal Processing, pp. 297-307, vol.82, no.2, 2015

TaeYoon An, KyeongKeun Choe, Kee-Won Kwon, and SoYoung Kim, "Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance,"Journal of Semiconductor Technology and Science, pp.525-536, vol.14, no.5, Oct. 2014

NamKyoung Kim, Jisoo Hwang and SoYoung Kim, "EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation" Journal of Semiconductor Technology and Science, pp. 471-477, vol.14, no.4, August, 2014 

NaHyun Kim, Wansoo Nah, SoYoung Kim, “Immunity Test for Semiconductor Integrated Circuits Considering Power Transfer Efficiency of the Bulk Current Injection Method,” Journal of Semiconductor Technology and Science, pp. 202-211, vol.14, no.2, Apr, 2014

Jongmin Kim, Duc Long Luong, Wansoo Nah, SoYoung Kim, “Measurement of Multi-Port S-Parameters using Four-Port Network Analyzer,” Journal of Semiconductor Technology and Science, pp. 589-593, vol.13, no.6, Dec., 2013

Bob Pu, Taeho Kim,  Jong-hyeon Kim,  SoYoung Kim, and Wansoo Nah, "Estimation of Transferred Power from a Noise Source to an IC with Forwarded Power Characteristics,"," Journal of Electromagnetic Engineering and Science, vol. 13, no. 4, pp233-239, Dec. 2013

Jeongha Park, Oh, S., SoYoung Kim, Wong, H.P., Wong S. S. “Impact of III–V and Ge Devices on Circuit Performance,”  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1189 – 1200, vol 21, issue 7, July, 2013.

KwangWon Lee, TaeYoon An, SoYeon Joo, Kee-Won Kwon, and SoYoung Kim, “Modeling of Parasitic Fringing Capacitancein Multifin Trigate FinFETs,” IEEE Transactions on Electron Devices, pp. 1786 - 1789, vol. 60, no. 5, May, 2013

SangKeun Kwak, Wansoo Nah and SoYoung Kim, “Electromagnetic Susceptibility Analysis of I/O Buffers Using the Bulk Current Injection Method,” Journal of Semiconductor Technology and Science, pp. 114-126, vol.13, no.2, Apr, 2013

Hongjin Kim, SoYoung Kim and Kang-Yoon Lee, " A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-SS Application,"Journal of Semiconductor Technology and Science, pp. 114-126, vol.13, no.2, Apr, 2013 

Hak-Tae Lee, Larry A. Meyn and SoYoung Kim,  "Probabilistic Safety Assessment of Unmanned Aerial System Operations", Journal of Guidance, Control, and Dynamics, pp. 610-617, vol. 36, no. 2, Mar, 2013

HyungGu Park, SoYoung Kim and Kang-Yoon Lee, "A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS," Analog Integrated Circuits and Signal Processing, pp. 507-515, vol.74, no.3, 2013

Hongjin Kim, SoYoung Kim and Kang-Yoon Lee, "Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application,"Analog Integrated Circuits and Signal Processing, pp. 599-612, vol.74, no.3, 2013

SangKeun Kwak, YoungSic Jo, JeongMin Jo, and SoYoung Kim, “Power Integrity and Shielding Effectiveness Modeling of Grid Structured Interconnects on PCBs ,” Journal of Semiconductor Technology and Science, pp. 320-330, vol. 12, no.3, Sep, 2012

Singh, R.,Jong-Kwan Woo, Hyunjoong Lee, So Young Kim, Suhwan Kim, “Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 749-762, vol. 59,  issue 4, Apr, 2012

International Conferences 

KyeongKeun Choi, TaeYoon Ahn and SoYoung Kim, "Accurate Fringe Capacitance Model Considering RSD and Metal Contact for Realistic FinFET and Circuit Performance Simulation", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp 256 – 259, Sept, 2014

KyungSoo Kim, Wansoo Nah, SoYoung Kim, “Noise-immune Design of Schmitt Trigger Logic Gate using DTMOS for Sub-threshold Circuits,”  IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), pp 83-88, Dec., 2013 Best student paper award

TaeYoon An, SoYoung Kim, “3-D Modeling of Fringing Gate Capacitance in Gate-all-around Cylindrical Silicon Nanowire,”  International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp 256 – 259, Sept, 2013.

HaiAu Huynh, KyungSoo Kim, WanSoo Nah, SoYoung Kim, “EMC/EMI Verification Methodology for Semi-Custom Design,” Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility(APEMC), pp 177-180, May, 2013

Namkyoung Kim, Nahyun Kim, Jisu Hwang, Jungmin Kim, SoYoung Kim, “EMI Prediction in Slew Rate Controlled Switching I/O Buffers,” Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility(APEMC), pp 181-184, May, 2013

국내 저널 

1. 정승익, 김소영, “LNA 설계를 통한 FinFETRC 기생 압축 모델 정확도 검증,” 전자공학회 논문지, 2016.11

 

2. 장문용, 김소영, “멀티 핀/핑거 FinFET 트랜지스터의 열 저항 해석과 모델링,” 전자공학회 논문지, 2016.08

 

3. 최경근, 권기원, 김소영, “정확한 기생 성분을 고려한 ITRS roadmap 기반 FinFET 공정 노드별 회로 성능 예측.”, 전자공학회 논문지, 2015.10

 

4. 최성식, 권기원, 김소영, “Tri-gate FinFETfin 및 소스/드레인 구조 변화에 따른 소자 성능 분석.”, 전자공학회 논문지, 2014.07

 

5. 이순철, 권기원, 김소영, “FinFET 게이트 저항 압축 모델 개발 및 최적화.” 전자공학회 논문지, 2014.08

 

6. 장익찬, 김진태, 김소영, “전류모드 논리 회로 기반의 고속 디지털 회로 디자인 최적화.” 전자공학회 논문지, 2014.11

 

7. 안태윤, 권기원, 김소영, “3차원적 전류 흐름을 고려한 FinFET의 기생 Source/Drain 저항 모델링.”, 전자공학회 논문지, 2013.10


8. 노석순, 권기원, 김소영, “3D Device simulator를 사용한 공정과 Layout에 따른 FinFET 아날로그 특성 연구.”, 전자공학회 논문지 2013.04