Resume

HOANG LE

hleusc @ gmail . com

EDUCATION

Ph.D. Computer Engineering (M.S. Electrical Engineering, 2009), University of Southern California, Los Angeles, California, 2011

Dissertation: High Performance Architectures for Packet Forwarding and String Pattern Matching (Advisor: Dr. Viktor K. Prasanna)

The research focused on (1) algorithms that are applicable to the network field of research, and (2) the use of lowpower memory, such as static random access memory (SRAM), combined with application-specific integrated circuit (ASIC) and/or field programmable gate array (FPGA) technology. The goals were to develop high-throughput, memory-efficient, and flexible algorithmic solutions for packet forwarding (used in core routers) and string pattern matching (used in network intrusion detection systems). The proposed solutions were evaluated using modern ASIC/FPGA platforms (using C/C++ and Verilog). The implementation results demonstrated superior performance over the state-of-the-art, with respect to the throughput and memory consumption. These results have been published in many top-tier conferences (FCCM, FPGA, INFOCOMM, FPL) and the prestigious IEEE Transactions on Computers.

Key research areas:

Tree-based IP lookup

Trie-based IP lookup

IP lookup in virtual routers

String pattern matching in NIDS

M.S. Computer Engineering, George Mason University, Fairfax, Virginia, 2007

Thesis: Reconfigurable Computing: A Design and Implementation Study of Elliptic Curve Method of Factoring Using SRC Carte-C and Celoxica Handel-C (Advisor: Dr. Kris Gaj)

The research explored different coding partitions of Elliptic Curve Method (ECM) of factoring using SRC Carte-C and Handel-C. Two code partitioning approaches have been implemented (in C/C++ and VHDL) and examined using the appropriate development environments, SRC Carte and Celoxica DK4 Development Kit. Similarities, differences and tradeoffs among the investigated languages and partitioning styles were also analyzed. The results have been published in CHES and later in IEEE Transactions on Computers.

B.S. Computer Engineering, Summa Cum Laude, George Mason University, Fairfax, Virginia, 2005

HIGHLIGHTS

  • Algorithms, data structures

  • Software-defined network

  • High-level simulation

  • Algorithm design, algorithm mapping on various hardware platforms (Multi/Many-Core, FPGA, ASIC)

  • Software/hardware co-design

  • Memory and energy-efficient data structures

  • High-performance and low-power architectures

RESEARCH INTERESTS

  • Network: Software-defined Network, High-Level Simulation, Cyber Security, Traffic Classification, High-Speed Routers, Virtualization

  • Extreme scale systems/architectures: Abstract Machine Models, Task Parallelism/Scheduler, Software/Hardware Co-design, Asynchronous Computation, Multi-level Memory Systems, Fast-Memory Structures

  • Hardware security: Secure Embedded Systems, Cryptographic Hardware

  • Computer vision: Image Processing, Object Detection and Tracking

  • Cognitive systems: Bayesian networks, Neural networks

INDUSTRY POSITIONS

Software Engineer, October 2015 - present

Google Irvine

Staff Design Engineer, September 2014 - October 2015

Xilinx Inc., Packet Processing Group, San Jose, CA

  • Software-defined network: Worked in a team to develop and implement 100+ Gbps packet processors on FPGAs; compile and generate micro-codes for programmable architectures; support incremental firmware updates.

  • High-level simulation: Generated high-level model in SystemC, C++ and TLM to simulate the behavior and correctness of software-defined network systems.

Senior Member of Technical Staff, June 2013 - September 2014

Sandia National Laboratories, Scalable Computer Architectures, Albuquerque, NM

    • Extreme Scale Systems/Architectures: Worked in a team to analyze the major challenges of mainstream computing technology and lay the ground work for overcoming them. Focused on the abilities to perform computations of both traditional and emerging applications. Produced abstract machine models of the future architecture for co-design centers to aid both software developers and hardware architects.

    • Adaptive Fast-Memory Structures: Proposed to investigate the benefits and feasibility of the fast-memory structure, which is the unified architecture between cache and scratchpad memories, from both software and hardware standpoints.

    • Task Parallelism/Scheduler: Worked in a team to explore the benefits of OpenMP/MPI over-decomposition task parallel approach (as opposed to the traditional data parallelism) to overcome the deficiency in the current Bulk Synchronous Parallel (BSP) programming model.

    • Next Generation Memory Technology: Worked in a team to investigate the next generation memory technologies (i.e. Hybrid Memory Cube) and in-memory processing to (1) avoid nonproductive data movement by moving computation closer to the data and (2) reduce the cost of data movement by eliminating or hiding overheads.

Inventor / Chief Scientist, February 2001 – present

DCS (Dynamic Computing Solutions), Columbia, MD

    • Expert in document imaging processing and data conversion: Over 10 years of experience.

    • Author of Ingressor (www.ingressor.com): A solution to the problem of fixing a corrupted Microsoft Outlook nickname cache without deleting all the entries. In addition to allowing search and edit nickname cache entries, this program will export the cache for sharing or backup and import data to pre-load the nickname cache with important addresses.

    • Inventor of PerfectScan (www.perfectscan.com): A unique image enhancement solution that has been acknowledged as the best in the industry. PerfectScan has been developed based on the early visual path processing and recognition models found in the human visual system. Instead of processing an image at the pixel level, PerfectScan takes it further and analyzes the entire image using a set of cognitive-based algorithms. These neural-inspired algorithms are tuned specifically to reduce noise, achieve perfect gamma correction, and obtain optimal image clarity. The end result is an output image that was never before thought possible.

Computer Scientist, September 2011 - June 2013

Irvine Sensors Corporation, Cognitive Systems, Costa Mesa, CA

    • Responsibilities: Writing proposals to DoD agencies; Designing memory efficient data structures, high-speed, and low-power architectures; Designing and mapping algorithms on hardware (FPGAs, GPGPUs, and manycore CPUs)

    • Real-Time Hyper-spectral Cognitive Processor: Worked in a team to develop a system to detect anomalies in as set of hyper-spectral and visible images. Developed matching and cross-model correlation algorithms for the system in software using C++. The software also interfaces with the accelerator hardware, which includes 6 Xilinx Virtex6 devices, using vendor’s provided APIs. This processor has demonstrated simultaneous spatial, color, and hyper-spectral cognitive processing operating on visual, thermal, and hyper-spectral imaging data sets in real time with low latency.

    • Ground Tracking Orientation Sensor System: Prototyped a device that allows weapon navigation in a GPS-denial environment. Developed the navigating algorithm based on feature matching and the mathematics model. The system satisfied the extreme low-power and good accuracy requirements.

    • High-Performance Distributed Cognitive Video Surveillance System: Worked in a team to develop a solution is to exploit advanced, high performance, cognitive-inspired processing techniques (e.g. adaptive saliency, cross-modal correlation, and supervised/unsupervised learning) that accurately emulate how the human visual path interprets imagery. Led the system exploration study to develop the specification of the system and chose the appropriate architecture. Developed algorithms for cognitive search, classification, and recognition processing.

Member of Security Group (research), Summer 2007, 2008, 2009, and 2010

Irvine Sensors, Business Security Department, Costa Mesa, CA

    • Network Security (SNORT on FPGA) (Summer 2010): Snort is an open-source intrusion prevention system capable of real-time traffic analysis and logging. Hence, it relies extensively on high-speed pattern matching of threat signature against those previously stored in a database. The focus was to implement the key pattern matching kernel on FPGAs for improved performance.

    • Memory Device Erasure Module (Anti-tamper) (Summer 2009): Worked on a secure memory device that could erase critical contents of a memory when an unauthorized tampering with the device or module is detected. Worked on both the hardware and software (C++) for this device. This device was commercially manufactured and sold successfully to several defense and security companies.

    • Securing Embedded Systems (Summer 2008): Reviewed critical embedded systems code in a “white hat” effort to detect and exploit weaknesses. Designed and implemented numerous attack vectors and found some key vulnerabilities.

    • High-speed TCAM on FPGA (Summer 2007): Designed and developed a module to emulate TCAM (ternary content addressable memory) using FPGAs to achieve the similar functionality a substantially lower power budget.

Computer Programmer, December 1998 – February 2001

M.S.I. LASON, Beltsville, MD

    • Data Archiving: Wrote script for data archiving using Captaris Alchemy.

    • Image Processing and Data Conversion Applications: Developed ASCII and EBCDIC character-code conversion; Variable record/line-delimiter and fixed-length record/line delimiter conversion; Image format conversion; TIFF image enhancement and processing; Database (MS SQL and Oracle) applications.

ACADEMIC POSITIONS

Graduate Research Assistant

  • Parallel Computing Group, University of Southern California, Los Angeles, CA, August 2007 – August 2011

    • Research: High-Speed Routers and Network Security

  • Crypto Lab, George Mason University, Fairfax, VA, January 2006 – May 2006

    • Research: Cryptography with reconfigurable computers, e.g. SRC-6 from SRC Computers

Graduate Teaching Assistant

    • USC Electrical Engineering Department, Los Angeles, CA, August 2007 – December 2009

      • EE201 - Introduction to Digital Circuits

      • EE357 - Basic Organization of Computer Systems

      • EE677 - VLSI Architectures and Algorithms

    • George Mason University, Fairfax, VA, January 2006 – May 2006

      • ECE448 - FPGA and ASIC Design with VHDL

PUBLICATIONS

Journals

    1. Oguzhan Erdem, Aydin Carus, and Hoang Le, “Value-Coded Trie Structure for High-Performance IPv6 Lookup”, The Computer Journal doi:10.1093/comjnl/bxt153, First published online:January 12, 2014

    2. Oguzhan Erdem, Aydin Carus, and Hoang Le, “Large-Scale SRAM-Based IP Lookup Architectures Using Compact Trie Search Structures”, The International Journal on Computers & Electrical Engineering, available online 1 November 2013, ISSN 0045-7906, http://dx.doi.org/10.1016/j.compeleceng.2013.10.011. (http://www.sciencedirect.com/science/article/pii/S0045790613002590).

    3. Hoang Le and Viktor K. Prasanna, “A Memory-Efficient and Modular Approach for Large-Scale String Pattern Matching”, IEEE Transactions on Computers, vol. 62, pp. 844-857, 2013.

    4. Hoang Le and Viktor K. Prasanna, “Scalable Tree-based Architectures for IPv4/v6 Lookup Using Prefix Partitioning”, IEEE Transactions on Computers, vol. 61, pp. 1026-1039, 2012.

    5. Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi, and Marcin Rogawski, “Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve”, IEEE Transactions on Computers, vol. 59, pp. 1264-1280, 2010.

Conferences

    1. James Ang, Richard Barrett, Robert Benner, Daniel Burke, Cy Chan, Jeanine Cook, David Donofrio, Simon Hammond, K. Scott Hemmert, Suzanne Kelly, Hoang Le, Vitus Leung, David Resnick, Arun Rodrigues, John Shalf, Dylan Stark, Didem Unat and Nicholas Wright, “Abstract Machine Models and Proxy Architectures for Exascale Computing”, In Proc. of the First International Workshop on Hardware-Software Co-design for High Performance Computing (Co-HPC), November 2014 (In conjunction with SC’14 and in collaboration with ACM SIGHPC).

    2. Kiran Kumar Matam, Hoang Le, and Viktor K. Prasanna, “Evaluating Energy Efficiency of Floating Point Matrix Multiplication on FPGAs”, In Proc. of the 17th Annual Internaltional Conference on High Performance Extreme Computing Conference 2013 (HPEC ‘13), September 2013.

    3. Kiran Kumar Matam, Hoang Le, and Viktor K. Prasanna, “Energy Efficient Architecture for Matrix Multiplication on FPGAs”, In Proc. of the 23rd Annual International Conference on Field-Programmable Logic and Applications 2013 (FPL '13), September 2013.

    4. Ren Chen, Hoang Le, and Viktor K. Prasanna, “Energy Efficient Parametrized FFT Architecture”, In Proc. of the 23rd Annual International Conference on Field-Programmable Logic and Applications 2013 (FPL '13), September 2013.

    5. Oguzhan Erdem, Aydin Carus, and Hoang Le, “Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs”, In Proc. of the 2012 International Conference on ReConFigurable Computing and FPGAs (ReConfig '12), December 2012.

    6. Oguzhan Erdem, Hoang Le and Viktor K. Prasanna, “Hierarchical Hybrid Search Structure for High Performance Packet Classification”, In Proc. of the 31th Conference on Computer Communications (INFOCOM '12), March 2012.

    7. Lu Sun, Hoang Le, and Viktor K. Prasanna, “Optimizing Decomposition-based Packet Classification Implementation on FPGAs”, In Proc. of the 2011 International Conference on ReConFigurable Computing and FPGAs (ReConfig '11), December 2011.

    8. Oguzhan Erdem, Hoang Le, and Viktor K. Prasanna, “Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs”, In Proc. of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’11), September 2011.

    9. Oguzhan Erdem, Hoang Le, and Viktor K. Prasanna, “Clustered Parameterized Hierarchical Search Structure for Large-Scale Packet Classification on FPGA”, In Proc. of the 21th Annual International Conference on Field-Programmable Logic and Applications 2011 (FPL '11), September 2011.

    10. Thilan Ganegedara, Hoang Le, and Viktor K. Prasanna, “Towards On-the-fly Incremental Updates for Virtualized Routers on FPGA”, In Proc. of the 21th Annual International Conference on Field-Programmable Logic and Applications 2011 (FPL '11), September 2011.

    11. Hoang Le, Weirong Jiang, and Viktor K. Prasanna, “Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression”, In Proc. of the 19th IEEE Symposium on Field Programmable Custom Computing Machines 2011 (FCCM '11), May 2011.

    12. Hoang Le, Thilan Ganegedara and Viktor K. Prasanna, “Memory-Efficient and Scalable Virtual Routers Using FPGA”, In Proc. of the Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '11), Feb 2011.

    13. Hoang Le and Viktor K. Prasanna, “High-Throughput IP-Lookup Supporting Dynamic Routing Tables using FPGA”, In Proc. of the International Conference on Field-Programmable Technology (FPT '10), Dec 2010.

    14. Hoang Le and Viktor K. Prasanna, “A Memory-Efficient and Modular Approach for String Matching on FPGAs”, In Proc. of the 18th IEEE Symposium on Field Programmable Custom Computing Machines 2010 (FCCM '10), April 2010.

    15. Hoang Le, Yi-Hua E. Yang and Viktor K. Prasanna, “Memory Efficient String Matching: A Modular Approach on FPGAs”, In Proc. of the 18th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '10), February 2010.

    16. Yi-Hua E. Yang, Hoang Le and Viktor K. Prasanna, “High Performance Dictionary-Based String Matching for Deep Packet Inspection”, In Proc. of the 29th Conference on Computer Communications (INFOCOM '10), March 2010.

    17. Hoang Le and Viktor K. Prasanna, “Scalable High Throughput and Power Efficient IP-Lookup on FPGA”, In Proc. of the 17th IEEE Symposium on Field Programmable Custom Computing Machines 2009 (FCCM '09), April 2009.

    18. Hoang Le, Weirong Jiang, and Viktor K. Prasanna, “Scalable High-Throughput Sram-Based Architecture for IP-Lookup Using FPGA”, In Proc. of the 18th Annual International Conference on Field-Programmable Logic and Applications 2008 (FPL '08), September 2008

    19. Hoang Le, Weirong Jiang, and Viktor K. Prasanna, “A SRAM-based Architecture for Trie-based IP Lookup Using FPGA”, In Proc. of the 16th Annual IEEE Symposium on Field Programmable Custom Computing Machines 2008 (FCCM '08), April 2008.

    20. Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi, “Implementing the elliptic curve method of factoring in reconfigurable hardware”, In Proc. CHES - Yokohama, Japan, pp. 119-133, Oct 2006 (also In Proc. of SHARCS - Cologne, Germany, Apr 2006, 28 pages).

PROFESSIONAL SERVICES

  • Reviewer:

    • Conferences: FCCM, FPGA, ANCS, ReConfig, FPL, FPT, IPDPS

    • Journals: IEEE TC, IEEE VLSI, ACM TRES, The Computer Journal

  • Technical Program Committee:

    • ANCS (2012, 2014, 2015), AICT (2013, 2014), ICPADS 2013, IPDPS 2014, FCCM (2014, 2015)

  • Publication Co-Chair:

    • HiPC (2012, 2013, 2014)

  • Publicity Co-Chair

    • ParLearning 2014 (IPDPS 2014)

  • Proceedings Chair

    • ANCS 2014

PROFESSIONAL MEMBERSHIPS

  • IEEE Member

  • ACM Member

  • Tau Beta Epsilon

  • Eta Kappa Nu Honor Society

HONORS AND AWARDS

  • Summa Cum Laude

  • Best TA Award

  • Chairman Award

  • Eta Kappa Nu and Tau Beta Epsilon Associations Award

  • Dean’s list

  • Presidential Scholars Award

  • National Dean’s List

  • Honor Rolls

  • Achievement Award in Physics (Best Student Physics Award)

  • Achievement Award in Mathematics (Best Student Mathematics Award)

  • Best Extended Learning Institute (ELI) Discipline Student

Updated May 1, 2015