EDUCATION Doctor of Philosophy in Electrical Engineering (Mar. 1993 - Feb. 1998) Korea Advanced Institute of Science and Technology, Daejon, KoreaDissertation: Reduction of Parasitic Capacitance in Heterojunction Bipolar Transistor and its Monolithic Integration with Field Effect Transistor
Korea Advanced Institute of Science and Technology, Daejon, KoreaThesis: Design and Fabrication of Monolithic Feedback Amplifier Bachelor of Science in Electrical Engineering (Mar. 1987 - Feb. 1991) Korea Advanced Institute of Science and Technology, Daejon, KoreaGraduated Summa Cum Laude
Kwangwoon University, Dept. Electronics Convergence Engineering, Seoul (Sept. 2003 – Present) Professor, High-Speed Integrated Circuit and System Lab. CMOS RF Transceivers for wireless communications, RF/Analog IC design, Microwave and millimeter-wave integrated circuit design, High-speed analog circuit design Teaching courses on RF/analog/digital/microwave integrated circuit design, wireless communication transceivers and system.
Visiting Faculty: RF/Analog ASIC Engineering, Involved in the next-generation RF transceiver front-end design. The multiband front-end module includes switch bank and wideband LNA, all of which should be integrated on SOI substrate. Designing active feedback LNAs for wideband/multiband diversity receive path.
Senior Engineer: Involved in the development of GSM/WCDMA multi-mode quad-band RF transceiver (RTR6250) in SiGe BiCMOS technology, technically in charge of GSM transmitter design of offset phase-locked loop (OPLL) type. Design experiences cover the most key RFIC’s as well as the top-level chip design for both of CDMA and GSM RF transceiver. Also working closely on system level design for CDMA and GSM standards as well as the 3G wireless communications. In the GSM Tx design, developed and published a new analysis method for the spectral spreading of a GMSK signal so that it helps specify the distortion requirements of a transmitter to meet the 400 kHz emission mask.
Postdoctoral Researcher and Lecturer: Advisor: Prof. Frank Chang. Three major projects First; High-speed digital I/O interface based on a novel RF/wireless inter- and intra-chip interconnect concept. Demonstrated 2Gbps RF-interconnect prototype in 0.18um CMOS based on capacitive coupling and 10-GHz RF modulation. Design involved 10 GHz RF direct conversion transceiver and CDMA baseband modem. Also involved in the 2.7Gbps CDMA-based high-speed interchip interconnect in CMOS. Second; Dual-band (6- and 9-GHz) direct-conversion transceiver IC design in SiGe BiCMOS for a reconfigurable aperture antenna (funded by DARPA). Developed a 1.8-V 6/9-GHz Reconfigurable Dual-Band Quadrature LC VCO in SiGe BiCMOS Technology with a switching time of 3.6 nsec. Third; designed a frequency synthesizer at 5.2GHz for IEEE802.11a using 0.25um CMOS. Also taught EE115B Analog Electronic Circuits II in Fall 2001as a Lecturer.
Senior Engineer: Involved in developing PCS/Cellular RF chips (KB8671/72) and baseband analog processor (KB8656/57/58 - completed transfer to volume production) using 0.5um BiCMOS technology for CDMA/AMPS cellular phones. Especially designed the following blocks: RxAGC with low current consumption (8mA), TxAGC with varying current consumption and high ACPR, 500MHz LC-tuned VCO with low phase noise of 115 dBc/Hz @ 100kHz, Analog quadrature modulator/demodulator. In addition, involved in design of the following blocks: low noise amplifier with 2 dB noise figure and +6 dBm IIP3, gilbert-cell mixer, CDMA/FM DAC & ADC, gm-C filters, Charge-pump PLL. For the development of the above chipsets, achieved in-depth knowledge about the CDMA system - budget analysis for RF front end, system architecture, CDMA coding method, digital modulation scheme, interface with mobile station modem.
Doktorand: Advisor: Dr. Helmut Leier. Developed an InP/InGaAs HBT process using polyimide planarization and an AlInAs/InGaAs HBT process using air-bridge process. Developed InP/InGaAs HBT for the first time at Daimler Research Center. Devices showed fT of 60 GHz and fMAX of 140 GHz. Invented and devised a new device structure for reduced base-collector capacitance which got a European and US patent. Investigated the emitter size effects on fT and proposed a formula for the relation. Developed 27-GHz oscillator using the fabricated transistors.
Internship: Involved in developing a X-band T/R module for DBS application using 0.5 um GaAs MESFET technology. Designed an LC-tuned voltage controlled oscillator. Investigated various VCO topologies with respect to phase noise and power consumption.
Graduate Student Researcher: Advisor : Prof. Young-Se Kwon. Conducted research in the following areas : Developed GaAs MMIC LNA at 6 GHz using Triquint foundry (1991). Developed GaAs MESFET MMIC Library - active and passive devices using the KAIST process. Much efforts has been done on developing and stabilizing the infant MMIC process (1992). Using the in-house process, developed various GaAs MESFET MMIC’s - Feedback amplifier with 5GHz-BW (1992), Wideband amplifier with 10 GHz-BW(1993), 2GHz VCO(1994), Mixer & Power Combiner (1995). Developed a cascode-type LNA for DBS using InGaAs p-HEMT technology(1997). As a doctoral research, developed a novel structure for monolithically integrating AlGaAs/GaAs HBT and GaAs FET (1994 - 1996) on the same substrate. Extensive experience in Device technology and epitaxial growth using MOCVD. All the epi-layers for the fabrication were grown by myself. Investigated the macro-step formation mechanism during the epi-growth on the vicinal substrate using an atomic force microscope (1996).
University of California at Los Angeles, Electrical Engineering Department, as a Lecturer, EE115B Analog Electronic Circuits II, Fall 2001 Kwangwoon University, Seoul, Korea, as a Professor since Fall 2003, Microelectronic circuits, Analog Integrated Circuit Design, Digital Integrated Circuit Design, RF Integrated Circuit Design, Special topics in Integrated Circuit Design, Advanced RF Circuits and Systems.
CMOS RF integrated circuits and transceivers for wireless communications
Co-recipient of Best Paper Award by LG Electronics for the paper entitled “Design of a 40GHz PLL Frequency Synthesizer with Wide Locking Range ILFD in 65nm CMOS” presented at The 2015 International SoC Design Conference, Jeju, Korea, Nov. 3, 2015.
PROFESSIONAL ACTIVITIES Technical Program Committee Member - IEEE International Solid-State Circuits Conference (ISSCC), RF subcommittee, 2015 - Present- IEEE VLSI Circuit Symposium, Technical Program Committee, 2016 - Present- IEIE RF Integrated Circuits Technology Workshop, Executive Committee Chair, 2014 - Present- IEIE SoC Conference, Technical Program Committee, 2007 - Present- International SoC Conference (ISOCC), TPC Vice Chair, 2014 and 2015- IEEE Asian Solid-State Circuits Conference (A-SSCC), RF subcommittee, 2007 – 2012- IEEE Int. Midwest Symp. on Circuits and Symposium (MWSCAS), RF track chair, 2011- Korean Semiconductor Conference (KCS), RF/Analog design subcommittee, 2006 - 2008 - IEEE Transactions on Microwave Theory and Technique- IEEE Microwave and Wireless Component Letters- IEEE Transactions on Circuits and Systems I & II- IEEE Journal of Solid-State Circuits- IEEE International Symposium on Circuits and Systems (ISCAS)
- Journal of Semiconductor Technology and Science, “Special Issue on RF Integrated Circuit Technology
- Senior Member, IEEE, USA, 1998 – present (M’98-SM’10)- Institute of Electronics, Information and Comm. Engineers (IEICE), Japan, 2009 - present- Institute of Electronics Engineers of Korea (IEEK)- Korea Electromagnetic Engineering Society (KEES)- Korea Institute of Communication and Science (KICS) |
