MC6809 max board

Bit of introduction

MC6809 8 bit Motorola processors was one of the most advanced in its time. It comes in various versions (speed) including a Hitachi 3 MHz (C type). Having few 6809P chips laying around I set out to create a minimal system, including a peripheral chip (PIO). Following is a prototype that I got working  which is minimal in design in having basically 5 main chips and TTL-USB adapter for comms to a PC. This project is ongoing and where possible I used particular IC's (like GAL's) to minimize the construction and size of the design.

Prototype Board

It mainly consist of the 6809P chip (1MHz), 6821 peripheral chip (PIO), Dallas DS1249AB-100 NVRam chip, 6850 ACIA serial chip and 24pin Atmel PLD chip to provide some of the decoding and interfacing. Additional things on the board are 14pin 1.8MHz resonator (for 6850 comms), 4 MHz crystal (for system clock, divide by 4, to give 1MHz clock). Flying wires are leads to  a TTL to USB converter that connects to USB port of a PC. Example monitor code is SBUG v1.8 and XBasic (TSC Extended Basic) programming language that needs Flex sys files to run. Gal chip used is Atmel ATF22V10CQ/CQZ. No particular reason for this one (as any other gal22v10 chip will do) ..  but you can easily get them from RS components and not that expensive. I will provide the .pld and .jed file for the code to program these. See notes later on.

Prototype board was constructed using a perforated/single solder-pin  type board with a bank of tracks to place the IC's. Wiring was soldered point to point using  wire wrap wire  and also banks of IDC type pins for wire wrapping from top of the board (click on picture for larger image). After initial mounting of the components and testing for shorts etc the board was ready for use.

Power consumption

When powered up the board draws about 270mA. See pic below.  Note when using the PIO chip and connections to it ..current consumption would increase... so make appropriate allowances for that.

Parts for construction

If you are an old micro buff you probably have some if not most parts to construct this mini board. In case you don't here is few suggestions for major parts.

  • 6809P  (P, A or B version) you might be lucky enough to get them from China supplies (via Alibaba  or Ebay website) prepared to wait 3-4 weeks at least.
  • Atmel pdl (GAL chip) try RS components.. usually very quick delivery. If you cannot program pld's I can supply the chip programmed.
  • 4, 6 or 8 MHz crystal (depending on chip type) ...try RS components or element14
  • 1.8432 MHz resonator   try RS components
  • TTL to USB adaptor, Many supplies from China via Ebay ..take 3-4 weeks
  • Dallas NVRAm chip try Ebay
  • 32 pin Ziff socket..for easy install of NVRAM
  • Also look through some forums like this one.

Circuit Design

It basically follows from some of the designs you will find on the web with simplification of decoding logic with a PLD chip, and use of a single NVRAM chip (both for ROM/RAM type function). For minimal system you would need at least a Monitor program, some RAM and an I/O comms. Simplest would be to have RS232 type comms that you can connect to a PC and communicate to the board via terminal type program.The  comms configuration settings are:

  • 115200 Baud
  • no parity
  • 8 bit
  • 1 stop bit
  • handshake none
I also added a 6821 chip to give extra 2 ports of I/O if needed. The PLD chip provides decoding and select chip lines as output ..together with ~WR and ~RD signals. Hence irrespective of the software.. you can configure the  appropriate ~CS lines to work OK for any memory mapping needed.

Schematic and component functions

Following is a schematic of the design (~2MHz version). It is using Diptrace software. Note I use point to point schematic (pin ID connections). It does reduce wires ..but for some people it gets bit harder to follow.

Other type of designs would have to be slightly different say as for "E" chip versions ...which have different type of clock input .. and hence pin connections ... and some chips like Hitachi clones can run at higher frequencies( C ver @ 3MHz). That can influence chips like the ACIA 6850  and 6821 PIO .. so make sure to use a faster version of them that run @ 2 MHz... this is not so much for serial, I/O output ..but the data bus end that connects to the microprocessor.

So if you use a B version of 6809 (2MHz) ..use the B versions of 6850 and 6821 respectively.. Also change the system clock to 8 MHz (gets divided by 4 for 2 MHz operation). ... or use a single chip version for all the clocks (7.3728MHZ)

Caution: As with any circuit diagrams it is up to you to recheck and make sure it is OK before proceeding to any construction. To best of my ability this is representation of what I have used. I've followed other circuit diagrams on the web, only to find some info was wrong. So please check pin outs (especially against datasheets) to make sure all connections are correct. If there is any errors please email me.

Download Schematic

Looking at the schematic here is bit of explanation of some of the component functions:
  • Resistors are basically pullup resistors for inputs to CPU that are not needed.
  • Led is just a power indicator for the board.
  • S1 (on board pb switch)is the manual reset input to 6809. Note also reset is provided from external input via terminal power block.
  • On 6821, A0-A1 used for on chip CR/DDR/Port addressing.
  • Chip selects for NVRAM and 6821 come from PLD.
  • PLD provides address decoding and  RD and WR signals .
  • I used the DS1249 chip which is a 256Kx8 bytes you only use 1/4 of it (64k)..(although you could bank switch ..if redesigning in future). The main reason for this NVRAM chip is that it is 32 pin and gives you more RAM for same amount of pins and is reasonably cheap. Plus it was the one I was able to program with Wellon programmer.

Here is update of PCB made recently from the prototype

PLD Function

PLD is used to provide address decoding and read/write signals. Additional unused pins could be used for future pld functions as needed  e.g. floppy controller chip select ..etc. For more info see Atmel website and WinCupl software.

The code for the PLD is shown below:

Name            6809 min board;
Partno          0001;
Revision        use only 64 k of Ram;
Date           10/5/15;
Designer        mc;
Company         mcoz;
Location        oz;
Assembly        manual;
Device          g22v10;

/** Inputs **/
pin [5..11] = [a15..a9] ;

pin 2 = e;
pin 3 = q;
pin 4 = rnw;
pin 13 = a8;

/** Outputs **/

pin 23 = !cs_sio;
pin 22 = !cs_ram;
pin 21 = !oe;
pin 20 = !wr;
pin 19 = !cs_pio;

/** Declarations and Intermediate Variable Definitions **/

field ioaddr= [a8..15];

cs_sio_eqn   = (ioaddr:[E0XX]);
cs_pio_eqn   = (ioaddr:[E8XX]);
cs_ram_eqn   = (ioaddr:[00XX..DFXX])# (ioaddr:[F0XX..FFXX]) ;

/** Logic Equations **/

cs_ram = cs_ram_eqn;
cs_sio = cs_sio_eqn;
cs_pio = cs_pio_eqn;

eq= e#q;
oe= e & rnw;
wr= !rnw & e & !(ioaddr:[F8XX..FFXX]);

Note (in above listing) the last wr equation..should write protect the F800-FFFF (SBUG Monitor Ram area) from being overwritten by wr signal at any sarge. Although spikes etc could rewrite any of the NVRAm area and hence would have to be programmed with a Programmer again.

The pin out for PLD is as follows:

View pld file

Download jed file

Memory Map

The memory map is as follows:
  • F800-FFFF SBUG (write protected)
  • C000-DFFF Partial Flex files  (not full OS system)
  • E000-E7FF ACIA
  • E800-EFFF  PIA
  • 0000- 4BFF approx Xbasic main program area
  • Note that any other map areas are basically FREE ram .. So when Xbasic runs it can get up to 28K Free to run user programs.
Download Full Memory code

Following download is a full 64k image from 0000-FFFF that has XBasic in lower part and Flex and SBUG in top part.
It is an image that already has run XBasic in cold start if you need to get back to it it is via $0003 warm startup address.

Testing the board

Obviously have the board connected to the PC and use appropriate comms software like Hyperterm (on XP) or RealTerm set to appropriate setting. Also set CAPS ON. (reduces errors). If all OK after pressing the RESET button the response should be "<" open bracket  ...where you can give monitor commands after that. Following is snapshot of sample commands in SBUG

From this point on you can explore some more of the monitor commands. Although part of Flex is loaded in RAM rest of the components like drives etc are not there do not use any of the commands that make use of these devices ... like U and D.

Saving and loading code (via terminal)

So for example to save above code you would issue command

SP 200-210 

 and before you press <CR>, set terminal program to capture file mode.. which will save text as it is output to the terminal.

Start capture mode and press <CR>

the listing should follow.. once character output had stopped ..Stop the capture ...

To see what is captured open the captured file with should look like something like this ...

To retrieve the code type in


and send the captured file as text using terminal program ..What you might need to do is delay the character and LF output to about 1ms so the board does not get swamped with incoming characters from the PC serial port. You can adjust the delay to smaller value till the sending of file stops working properly. Few ms+ is usually a safe bet.

Picture above shows loading of the file, listing  the code, running it and then listing the result of the addition program. So there you are ..plenty of things to be able to examine ..with minimal system configuration for 6809.