Project Details

The Prototype Hardware

The project is based on an Altera MAX10 FPGA. The current prototype setup consists of a standard Commodore 64 main-board where the SID chip has been replaced by an FPGA evaluation board (click for details). This eval-board is connected with some glue logic (mainly for level shifting) to the 28-pin SID socket of a Commodore 64 computer. This platform allows me to use the FPGASID directly in the target hardware. So I can do testing with real programs under real-time conditions.

On the right you see the prototype as on display on the Classic Computing 2015 in Thionville.

To make the testing of compatibility issues more comfortable I created a PCB that fits into the expansion port of the C64. This PCB carries the original SID. Once plugged into the expansion port, the second SID is controlled in exactly the same way as the FPGASID. The ultimate goal is to make the FPGASID and the original SID behave absolutely identical. To find this out I connected the sound output of the original and the surrogate to the left and right channel of a stereo amplifier. This way each difference in the sound output is clearly audible because any difference will break the "perfect" mono signal.


FPGASID (left) and original SID (right)

In this closeup you see how the original SID in the expansion slot is supplied with 12V power supply (yellow wire) and the SID's chip-select signal (black wire) as these are not available on the expansion port connector. The red cinch connector feeds the original SID's output signal to the right channel of a Stereo amplifier.

The FPGASID is the bigger PCB left of the modulator box. It resides directly in the SID 28-pin socket. The breadboard underneath is used for mechanical connection and it carries some level shifters to translate the 5V signals of the C64 to the 3.3V logic of the evaluation board. The audio connection of the FPGASID goes through the A/V connector of the C64 to the left channel of the stereo amplifier.

You can listen to such a comparison stereo signal here: TheLastV8. This song was one of the first songs I used to test the FPGASID implementation. In this audio file the left channel is the FPGASID and the right channel is the original SID. In this case both sources match pretty well. Mainly because this tune does not use any filtering. To give you an example how much the filtering differs from the original implementation you can listen to CaerAisling. This song is using a lot of filtering and you can hear that the filters do not match between left (FPGASID) and right (original SID) channel.

The Verilog Simulation is showing internal signals in full detail

Another method of design verification is
the Verilog simulation. For FPGAs this is the usual way of doing things. It does not require any hardware. The only thing that is needed is computation time on a fast PC. When a simulation is done, the Verilog code is executed by the simulation engine, rather than on a real FPGA. Since the FPGA is doing everything in parallel and the simulator is a software which is running sequentially, it becomes clear that the execution time of the simulation can become quite long. In our case it takes about one hour to simulate 4 seconds of real time (on an quadcore i5@3.1GHz). But on the other hand there are many advantages of simulation: You can check all internal signals you want in full detail. A thing that would be extremely difficult to do directly on the FPGA.

I did such a simulation just recently when I finalized the new filter implementation and had to find some nasty bugs. The result is an audiofile with the simulated signal from FPGASID on the left channel and the signal generated by the RESID library on the right channel. So basically two different simulation implementations are compared against each other. I took the same song as before: CaerAisling. I would say FPGASID is already quite close to RESID now. Please judge by yourself!

After some extensive debugging in simulation and a major change in the clocking scheme of the FPGA (details here), the resulting sound quality came even closer to the original 6581 SID. Here you find a sample of this achievement, recorded directly from the hardware. Again the same song, FPGASID on the left and the 6581 on the right. I am proud to say that this is the first time I personally have trouble identifying the source, when I don't know what I am listening to: FPGASID or 6581.

After this achievement some intense testing has started with a small number of test persons. The performance of FPGASID is checked against original 6581 devices with some selected test tunes.

One central element of these tests is the automated recording of SID tunes. This allows me to do new recordings of the test songs whenever a new FPGA release is ready. This is saving a lot of time. To do this I connected a NetIO board from Pollin to the FPGASID prototype and to the controlling PC. This allows me to control the prototype to play back SID tunes to make recordings on the PC.
Details on how this automation is working can be found here.

The NetIO board hooked up
to the FPGASID prototype.



The Next Prototype

The FPGASID prototype, based on the Altera evaluation board, has shown that the implementation of a SID replacement is feasible. So the time has come to go the next step now. A step to a new prototype that is no longer based on an evaluation board.

A hardware platform is required that should be much smaller in order to fit into a standard C64 (with the case properly closed of course). And with this new prototype it should be possible to do some field testing performed by early alpha testers. So the handling has to be easy enough for this purpose.

The development of this new prototype was supported by a second designer. Thomas did the complete PCB routing and helped a lot in reviewing the schematics and making design decisions for the new prototype. Internally we call our new baby the 'FPGASID_proto1'. 

The schematics and PCB-Layout was entirely done with KiCAD. This program is a very professional EDA tool. Suitable for simple and complex projects. It covers the full range from design entry on schematic level over PCB routing to production data generation. And it's completely free!


Here you see KiCAD in action.


The work on the prototype PCB is very advanced now. This allows the rendering of pictures that show, how the end product will finally look like.

The PCB has a size of 48 mm x 31 mm and will fit directly into the SID socket. Some extra wiring will be required to connect signals that are not available on the socket. These connections will be possible without soldering. A JTAG connector is present for debugging and flashing new FPGA code. And last, but not least, three LEDs will do some nice blinking when a tune is played help debugging complex FPGA bugs.

The PCB has 4 layers and carries a BGA version of the MAX10 FPGA. The finest structures measure only 100 µm and the vias have a hole of only 200 µm diameter. These parameters should make clear, that it's mandatory to produce the board at a high quality PCB maker. Unfortunately this is the point where home-brew technology ends.

Visualization of FPGASID_proto1.


 

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CaerAisling_FPGASID_rv40_vs_6581_0184.mp3
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CaerAisling_simulation_L-FPGASID_L-RESID.mp3
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TheLastV8_FPGASID_vs_6581_2383.mp3
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